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outerDataBits / innerDataBits should be per beat, not per block

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This commit is contained in:
Howard Mao 2015-10-21 11:31:13 -07:00
parent baf95533a4
commit 02d113b39f
1 changed files with 2 additions and 2 deletions
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uncore/src/main/scala/uncore.scala
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@ -20,14 +20,14 @@ trait HasCoherenceAgentParameters {
val outerTLId = p(OuterTLId) val outerTLId = p(OuterTLId)
val outerTLParams = p(TLKey(outerTLId)) val outerTLParams = p(TLKey(outerTLId))
val outerDataBeats = outerTLParams.dataBeats val outerDataBeats = outerTLParams.dataBeats
val outerDataBits = outerTLParams.dataBits val outerDataBits = outerTLParams.dataBitsPerBeat
val outerBeatAddrBits = log2Up(outerDataBeats) val outerBeatAddrBits = log2Up(outerDataBeats)
val outerByteAddrBits = log2Up(outerDataBits/8) val outerByteAddrBits = log2Up(outerDataBits/8)
val outerWriteMaskBits = outerTLParams.writeMaskBits val outerWriteMaskBits = outerTLParams.writeMaskBits
val innerTLId = p(InnerTLId) val innerTLId = p(InnerTLId)
val innerTLParams = p(TLKey(innerTLId)) val innerTLParams = p(TLKey(innerTLId))
val innerDataBeats = innerTLParams.dataBeats val innerDataBeats = innerTLParams.dataBeats
val innerDataBits = innerTLParams.dataBits val innerDataBits = innerTLParams.dataBitsPerBeat
val innerWriteMaskBits = innerTLParams.writeMaskBits val innerWriteMaskBits = innerTLParams.writeMaskBits
val innerBeatAddrBits = log2Up(innerDataBeats) val innerBeatAddrBits = log2Up(innerDataBeats)
val innerByteAddrBits = log2Up(innerDataBits/8) val innerByteAddrBits = log2Up(innerDataBits/8)