From 02d113b39fda1f47e141068e600a384a6f998e5f Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 21 Oct 2015 11:31:13 -0700 Subject: [PATCH] outerDataBits / innerDataBits should be per beat, not per block --- uncore/src/main/scala/uncore.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala index bfdbe681..d8f0683e 100644 --- a/uncore/src/main/scala/uncore.scala +++ b/uncore/src/main/scala/uncore.scala @@ -20,14 +20,14 @@ trait HasCoherenceAgentParameters { val outerTLId = p(OuterTLId) val outerTLParams = p(TLKey(outerTLId)) val outerDataBeats = outerTLParams.dataBeats - val outerDataBits = outerTLParams.dataBits + val outerDataBits = outerTLParams.dataBitsPerBeat val outerBeatAddrBits = log2Up(outerDataBeats) val outerByteAddrBits = log2Up(outerDataBits/8) val outerWriteMaskBits = outerTLParams.writeMaskBits val innerTLId = p(InnerTLId) val innerTLParams = p(TLKey(innerTLId)) val innerDataBeats = innerTLParams.dataBeats - val innerDataBits = innerTLParams.dataBits + val innerDataBits = innerTLParams.dataBitsPerBeat val innerWriteMaskBits = innerTLParams.writeMaskBits val innerBeatAddrBits = log2Up(innerDataBeats) val innerByteAddrBits = log2Up(innerDataBits/8)