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tilelink2 Nodes: rename RootNode => BaseNode

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This commit is contained in:
Wesley W. Terpstra 2016-09-29 14:34:52 -07:00
parent 754fcf9831
commit 02ce8c2ca4
4 changed files with 11 additions and 11 deletions
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4
src/main/scala/uncore/tilelink2/IntNodes.scala
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@ -23,13 +23,13 @@ object IntRange
case class IntSourceParameters(
range: IntRange,
nodePath: Seq[RootNode] = Seq())
nodePath: Seq[BaseNode] = Seq())
{
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
}
case class IntSinkParameters(
nodePath: Seq[RootNode] = Seq())
nodePath: Seq[BaseNode] = Seq())
{
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
}

2
src/main/scala/uncore/tilelink2/LazyModule.scala
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@ -9,7 +9,7 @@ abstract class LazyModule
{
protected[tilelink2] var bindings = List[() => Unit]()
protected[tilelink2] var children = List[LazyModule]()
protected[tilelink2] var nodes = List[RootNode]()
protected[tilelink2] var nodes = List[BaseNode]()
protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
protected[tilelink2] val parent = LazyModule.stack.headOption

12
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -32,7 +32,7 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data]
abstract class NodeImp[D, U, EO, EI, B <: Data]
extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
abstract class RootNode
abstract class BaseNode
{
// You cannot create a Node outside a LazyModule!
require (!LazyModule.stack.isEmpty)
@ -45,11 +45,11 @@ abstract class RootNode
def colour = "blue"
def omitGraphML = outputs.isEmpty && inputs.isEmpty
protected[tilelink2] def outputs: Seq[RootNode]
protected[tilelink2] def inputs: Seq[RootNode]
protected[tilelink2] def outputs: Seq[BaseNode]
protected[tilelink2] def inputs: Seq[BaseNode]
}
trait InwardNode[DI, UI, BI <: Data] extends RootNode
trait InwardNode[DI, UI, BI <: Data] extends BaseNode
{
protected[tilelink2] val numPI: Range.Inclusive
require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
@ -74,7 +74,7 @@ trait InwardNode[DI, UI, BI <: Data] extends RootNode
protected[tilelink2] def iConnect: Vec[BI]
}
trait OutwardNode[DO, UO, BO <: Data] extends RootNode
trait OutwardNode[DO, UO, BO <: Data] extends BaseNode
{
protected[tilelink2] val numPO: Range.Inclusive
require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
@ -106,7 +106,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
private val uFn: (Int, Seq[UO]) => Seq[UI],
protected[tilelink2] val numPO: Range.Inclusive,
protected[tilelink2] val numPI: Range.Inclusive)
extends RootNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
{
// meta-data for printing the node graph
protected[tilelink2] def outputs = oPorts.map(_._2)

4
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -149,7 +149,7 @@ case class TLManagerParameters(
sinkId: IdRange = IdRange(0, 1),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[RootNode] = Seq(),
nodePath: Seq[BaseNode] = Seq(),
// Supports both Acquire+Release+Finish of these sizes
supportsAcquire: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
@ -293,7 +293,7 @@ case class TLManagerPortParameters(
case class TLClientParameters(
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[RootNode] = Seq(),
nodePath: Seq[BaseNode] = Seq(),
// Supports both Probe+Grant of these sizes
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,