From 02ce8c2ca4b4e5f4e1a48e2c2bdce4fe945a1390 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 29 Sep 2016 14:34:52 -0700
Subject: [PATCH] tilelink2 Nodes: rename RootNode => BaseNode

---
 src/main/scala/uncore/tilelink2/IntNodes.scala   |  4 ++--
 src/main/scala/uncore/tilelink2/LazyModule.scala |  2 +-
 src/main/scala/uncore/tilelink2/Nodes.scala      | 12 ++++++------
 src/main/scala/uncore/tilelink2/Parameters.scala |  4 ++--
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala
index acf1cdc8..0d46300c 100644
--- a/src/main/scala/uncore/tilelink2/IntNodes.scala
+++ b/src/main/scala/uncore/tilelink2/IntNodes.scala
@@ -23,13 +23,13 @@ object IntRange
 
 case class IntSourceParameters(
   range:    IntRange,
-  nodePath: Seq[RootNode] = Seq())
+  nodePath: Seq[BaseNode] = Seq())
 {
   val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
 }
 
 case class IntSinkParameters(
-  nodePath: Seq[RootNode] = Seq())
+  nodePath: Seq[BaseNode] = Seq())
 {
   val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
 }
diff --git a/src/main/scala/uncore/tilelink2/LazyModule.scala b/src/main/scala/uncore/tilelink2/LazyModule.scala
index 8f4f0949..f85af894 100644
--- a/src/main/scala/uncore/tilelink2/LazyModule.scala
+++ b/src/main/scala/uncore/tilelink2/LazyModule.scala
@@ -9,7 +9,7 @@ abstract class LazyModule
 {
   protected[tilelink2] var bindings = List[() => Unit]()
   protected[tilelink2] var children = List[LazyModule]()
-  protected[tilelink2] var nodes = List[RootNode]()
+  protected[tilelink2] var nodes = List[BaseNode]()
   protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
   protected[tilelink2] val parent = LazyModule.stack.headOption
 
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index d65339df..9a4c0497 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -32,7 +32,7 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data]
 abstract class NodeImp[D, U, EO, EI, B <: Data]
   extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
 
-abstract class RootNode
+abstract class BaseNode
 {
   // You cannot create a Node outside a LazyModule!
   require (!LazyModule.stack.isEmpty)
@@ -45,11 +45,11 @@ abstract class RootNode
   def colour = "blue"
   def omitGraphML = outputs.isEmpty && inputs.isEmpty
 
-  protected[tilelink2] def outputs: Seq[RootNode]
-  protected[tilelink2] def inputs:  Seq[RootNode]
+  protected[tilelink2] def outputs: Seq[BaseNode]
+  protected[tilelink2] def inputs:  Seq[BaseNode]
 }
 
-trait InwardNode[DI, UI, BI <: Data] extends RootNode
+trait InwardNode[DI, UI, BI <: Data] extends BaseNode
 {
   protected[tilelink2] val numPI: Range.Inclusive
   require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
@@ -74,7 +74,7 @@ trait InwardNode[DI, UI, BI <: Data] extends RootNode
   protected[tilelink2] def iConnect: Vec[BI]
 }
 
-trait OutwardNode[DO, UO, BO <: Data] extends RootNode
+trait OutwardNode[DO, UO, BO <: Data] extends BaseNode
 {
   protected[tilelink2] val numPO: Range.Inclusive
   require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
@@ -106,7 +106,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
   private val uFn: (Int, Seq[UO]) => Seq[UI],
   protected[tilelink2] val numPO: Range.Inclusive,
   protected[tilelink2] val numPI: Range.Inclusive)
-  extends RootNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
+  extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
 {
   // meta-data for printing the node graph
   protected[tilelink2] def outputs = oPorts.map(_._2)
diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala
index 463ac2e3..71fd667e 100644
--- a/src/main/scala/uncore/tilelink2/Parameters.scala
+++ b/src/main/scala/uncore/tilelink2/Parameters.scala
@@ -149,7 +149,7 @@ case class TLManagerParameters(
   sinkId:             IdRange       = IdRange(0, 1),
   regionType:         RegionType.T  = RegionType.GET_EFFECTS,
   executable:         Boolean       = false, // processor can execute from this memory
-  nodePath:           Seq[RootNode] = Seq(),
+  nodePath:           Seq[BaseNode] = Seq(),
   // Supports both Acquire+Release+Finish of these sizes
   supportsAcquire:    TransferSizes = TransferSizes.none,
   supportsArithmetic: TransferSizes = TransferSizes.none,
@@ -293,7 +293,7 @@ case class TLManagerPortParameters(
 
 case class TLClientParameters(
   sourceId:            IdRange       = IdRange(0,1),
-  nodePath:            Seq[RootNode] = Seq(),
+  nodePath:            Seq[BaseNode] = Seq(),
   // Supports both Probe+Grant of these sizes
   supportsProbe:       TransferSizes = TransferSizes.none,
   supportsArithmetic:  TransferSizes = TransferSizes.none,