tilelink2 Nodes: rename RootNode => BaseNode
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@ -32,7 +32,7 @@ trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class RootNode
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abstract class BaseNode
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{
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// You cannot create a Node outside a LazyModule!
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require (!LazyModule.stack.isEmpty)
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@ -45,11 +45,11 @@ abstract class RootNode
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def colour = "blue"
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def omitGraphML = outputs.isEmpty && inputs.isEmpty
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protected[tilelink2] def outputs: Seq[RootNode]
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protected[tilelink2] def inputs: Seq[RootNode]
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protected[tilelink2] def outputs: Seq[BaseNode]
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protected[tilelink2] def inputs: Seq[BaseNode]
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}
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trait InwardNode[DI, UI, BI <: Data] extends RootNode
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trait InwardNode[DI, UI, BI <: Data] extends BaseNode
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{
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protected[tilelink2] val numPI: Range.Inclusive
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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@ -74,7 +74,7 @@ trait InwardNode[DI, UI, BI <: Data] extends RootNode
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protected[tilelink2] def iConnect: Vec[BI]
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}
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trait OutwardNode[DO, UO, BO <: Data] extends RootNode
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trait OutwardNode[DO, UO, BO <: Data] extends BaseNode
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{
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protected[tilelink2] val numPO: Range.Inclusive
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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@ -106,7 +106,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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private val uFn: (Int, Seq[UO]) => Seq[UI],
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protected[tilelink2] val numPO: Range.Inclusive,
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protected[tilelink2] val numPI: Range.Inclusive)
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extends RootNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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// meta-data for printing the node graph
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protected[tilelink2] def outputs = oPorts.map(_._2)
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