generate consts.vh from chisel source
This commit is contained in:
Yunsup Lee
parent
cfecd8832d
commit
02c08a156f
9
Makefrag
9
Makefrag
@ -22,14 +22,19 @@ timeout_cycles = 100000000
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# Verilog Generation
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#--------------------------------------------------------------------
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# VLSI Backend
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$(generated_dir)/$(MODEL).v: $(chisel_srcs)
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cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG)"
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cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG) --configDump"
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cd $(generated_dir) && \
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if [ -a $(MODEL).conf ]; then \
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$(mem_gen) $(generated_dir)/$(MODEL).conf >> $(generated_dir)/$(MODEL).v; \
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fi
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$(generated_dir)/consts.vh: $(generated_dir)/rocketchip.$(CONFIG).prm
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echo "\`ifndef CONST_VH" > $@
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echo "\`define CONST_VH" >> $@
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sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
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echo "\`endif // CONST_VH" >> $@
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$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
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cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
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2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 30ff8ebf6f2ff0583276b19ed9fa08295c8957d1
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Subproject commit 94650dae31260a2d48ef02d99389b1f392ddee43
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@ -7,10 +7,10 @@
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).v \
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$(generated_dir)/consts.vh \
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$(generated_dir)/memdessertMemDessert.v \
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$(base_dir)/vsrc/const.vh \
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$(base_dir)/vsrc/rocketTestHarness.v \
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$(base_dir)/vsrc/bram_mem.v \
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$(base_dir)/vsrc/backup_mem.v \
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# C sources
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@ -9,7 +9,7 @@ class DefaultConfig extends ChiselConfig {
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val topDefinitions:World.TopDefs = {
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(pname,site,here) => pname match {
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//HTIF Parameters
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case HTIFWidth => 16
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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@ -21,9 +21,9 @@ class DefaultConfig extends ChiselConfig {
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFTagBits => Dump("MEM_TAG_BITS", 5)
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
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//Params used by all caches
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case ECCCode => None
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@ -7,10 +7,10 @@
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).v \
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$(generated_dir)/consts.vh \
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$(generated_dir)/memdessertMemDessert.v \
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$(base_dir)/vsrc/const.vh \
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$(base_dir)/vsrc/rocketTestHarness.v \
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$(base_dir)/vsrc/bram_mem.v \
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$(base_dir)/vsrc/backup_mem.v \
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# C sources
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@ -1,4 +1,5 @@
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`define ceilLog2(x) ((x) > 2**30 ? 31 : \
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`define ceilLog2(x) ( \
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(x) > 2**30 ? 31 : \
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(x) > 2**29 ? 30 : \
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(x) > 2**28 ? 29 : \
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(x) > 2**27 ? 28 : \
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@ -31,7 +32,7 @@
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(x) > 2**0 ? 1 : 0)
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`ifdef MEM_BACKUP_EN
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module BRAMMem
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module BackupMemory
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(
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input clk,
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input reset,
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@ -40,7 +41,7 @@ module BRAMMem
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output mem_req_ready,
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input mem_req_rw,
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input [`MEM_ADDR_BITS-1:0] mem_req_addr,
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input [15:0] mem_req_tag,
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input [`MEM_TAG_BITS-1:0] mem_req_tag,
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input mem_req_data_valid,
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output mem_req_data_ready,
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@ -48,14 +49,14 @@ module BRAMMem
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output reg mem_resp_valid,
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output reg [`MEM_DATA_BITS-1:0] mem_resp_data,
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output reg [15:0] mem_resp_tag
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output reg [`MEM_TAG_BITS-1:0] mem_resp_tag
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);
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localparam DATA_CYCLES = 4;
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localparam DEPTH = 2*1024*1024;
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reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
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reg [15:0] tag;
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reg [`MEM_TAG_BITS-1:0] tag;
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reg state_busy, state_rw;
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reg [`MEM_ADDR_BITS-1:0] addr;
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@ -1,8 +0,0 @@
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`ifndef CONST_VH
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`define CONST_VH
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`define MEM_ADDR_BITS 34
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`define MEM_DATA_BITS 128
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`define MEM_TAG_BITS 10
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`endif // CONST_VH
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@ -1,7 +1,5 @@
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// Test harness for Rocket RISC-V Processor
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`define HTIF_WIDTH 16
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extern "A" void htif_init
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(
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input reg [31:0] htif_width,
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@ -233,7 +231,7 @@ module rocketTestHarness;
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.io_wide_resp_bits_tag(mem_bk_resp_tag)
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);
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BRAMMem mem
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BackupMemory mem
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(
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.clk(htif_clk),
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.reset(reset),
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