generate consts.vh from chisel source

Makefrag

@@ -22,14 +22,19 @@ timeout_cycles = 100000000
 # Verilog Generation
 #--------------------------------------------------------------------
 
-# VLSI Backend
 $(generated_dir)/$(MODEL).v: $(chisel_srcs)
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG)"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG) --configDump"
 	cd $(generated_dir) && \
 	if [ -a $(MODEL).conf ]; then \
 	  $(mem_gen) $(generated_dir)/$(MODEL).conf >> $(generated_dir)/$(MODEL).v; \
 	fi
 
+$(generated_dir)/consts.vh: $(generated_dir)/rocketchip.$(CONFIG).prm
+	echo "\`ifndef CONST_VH" > $@
+	echo "\`define CONST_VH" >> $@
+	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
+	echo "\`endif // CONST_VH" >> $@
+
 $(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
 	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
 

chisel

@@ -1 +1 @@
-Subproject commit 30ff8ebf6f2ff0583276b19ed9fa08295c8957d1
+Subproject commit 94650dae31260a2d48ef02d99389b1f392ddee43

fsim/Makefrag

@@ -7,10 +7,10 @@
 
 sim_vsrcs = \
 	$(generated_dir)/$(MODEL).v \
+	$(generated_dir)/consts.vh \
 	$(generated_dir)/memdessertMemDessert.v \
-	$(base_dir)/vsrc/const.vh \
 	$(base_dir)/vsrc/rocketTestHarness.v \
-	$(base_dir)/vsrc/bram_mem.v \
+	$(base_dir)/vsrc/backup_mem.v \
 
 # C sources
 

src/main/scala/PublicConfigs.scala

@@ -9,7 +9,7 @@ class DefaultConfig extends ChiselConfig {
   val topDefinitions:World.TopDefs = {
     (pname,site,here) => pname match {
       //HTIF Parameters
-      case HTIFWidth => 16
+      case HTIFWidth => Dump("HTIF_WIDTH", 16)
       case HTIFNSCR => 64
       case HTIFOffsetBits => site(CacheBlockOffsetBits)
       case HTIFNCores => site(NTiles)
@@ -21,9 +21,9 @@ class DefaultConfig extends ChiselConfig {
       case PermBits => 6
       case PPNBits => site(PAddrBits) - site(PgIdxBits)
       case VPNBits => site(VAddrBits) - site(PgIdxBits)
-      case MIFTagBits => 5
+      case MIFTagBits => Dump("MEM_TAG_BITS", 5)
-      case MIFDataBits => 128
+      case MIFDataBits => Dump("MEM_DATA_BITS", 128)
-      case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
+      case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
       case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
       //Params used by all caches
       case ECCCode => None

vsim/Makefrag

@@ -7,10 +7,10 @@
 
 sim_vsrcs = \
 	$(generated_dir)/$(MODEL).v \
+	$(generated_dir)/consts.vh \
 	$(generated_dir)/memdessertMemDessert.v \
-	$(base_dir)/vsrc/const.vh \
 	$(base_dir)/vsrc/rocketTestHarness.v \
-	$(base_dir)/vsrc/bram_mem.v \
+	$(base_dir)/vsrc/backup_mem.v \
 
 # C sources
 

vsrc/backup_mem.v

@@ -1,4 +1,5 @@
-`define ceilLog2(x) ((x) > 2**30 ? 31 : \
+`define ceilLog2(x) ( \
+(x) > 2**30 ? 31 : \
 (x) > 2**29 ? 30 : \
 (x) > 2**28 ? 29 : \
 (x) > 2**27 ? 28 : \
@@ -31,7 +32,7 @@
 (x) > 2**0 ? 1 : 0)
 
 `ifdef MEM_BACKUP_EN
-module BRAMMem
+module BackupMemory
 (
   input         clk,
   input         reset,
@@ -40,7 +41,7 @@ module BRAMMem
   output                      mem_req_ready,
   input                       mem_req_rw,
   input [`MEM_ADDR_BITS-1:0]  mem_req_addr,
-  input  [15:0]               mem_req_tag,
+  input [`MEM_TAG_BITS-1:0]   mem_req_tag,
 
   input                       mem_req_data_valid,
   output                      mem_req_data_ready,
@@ -48,14 +49,14 @@ module BRAMMem
 
   output reg                  mem_resp_valid,
   output reg [`MEM_DATA_BITS-1:0] mem_resp_data,
-  output reg  [15:0]          mem_resp_tag
+  output reg [`MEM_TAG_BITS-1:0] mem_resp_tag
 );
 
   localparam DATA_CYCLES = 4;
   localparam DEPTH = 2*1024*1024;
 
   reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
-  reg [15:0] tag;
+  reg [`MEM_TAG_BITS-1:0] tag;
   reg state_busy, state_rw;
   reg [`MEM_ADDR_BITS-1:0] addr;
 

vsrc/const.vh

@@ -1,8 +0,0 @@
-`ifndef CONST_VH
-`define CONST_VH
-
-`define MEM_ADDR_BITS 34
-`define MEM_DATA_BITS 128
-`define MEM_TAG_BITS 10
-
-`endif // CONST_VH

vsrc/rocketTestHarness.v

@@ -1,7 +1,5 @@
 // Test harness for Rocket RISC-V Processor
 
-`define HTIF_WIDTH 16
-
 extern "A" void htif_init
 (
   input reg [31:0] htif_width,
@@ -233,7 +231,7 @@ module rocketTestHarness;
     .io_wide_resp_bits_tag(mem_bk_resp_tag)
   );
 
-  BRAMMem mem
+  BackupMemory mem
   (
     .clk(htif_clk),
     .reset(reset),