riscv/rocket-chip
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Support retirement width > 1 in CSR file

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This commit is contained in:
Andrew Waterman 2014-01-24 16:36:36 -08:00
parent 267394d3cc
commit 0266c1f76a
3 changed files with 13 additions and 7 deletions
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2
rocket/src/main/scala/dpath_util.scala
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@ -98,7 +98,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val ptbr = UInt(OUTPUT, PADDR_BITS) val ptbr = UInt(OUTPUT, PADDR_BITS)
val evec = UInt(OUTPUT, VADDR_BITS+1) val evec = UInt(OUTPUT, VADDR_BITS+1)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = Bool(INPUT) val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
val cause = UInt(INPUT, conf.xprlen) val cause = UInt(INPUT, conf.xprlen)
val badvaddr_wen = Bool(INPUT) val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1) val pc = UInt(INPUT, VADDR_BITS+1)

2
rocket/src/main/scala/tile.scala
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@ -7,6 +7,7 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration, case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig, icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None, fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
retireWidth: Int = 1,
vm: Boolean = true, vm: Boolean = true,
fastLoadWord: Boolean = true, fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false, fastLoadByte: Boolean = false,
@ -30,6 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
implicit val icConf = confIn.icache implicit val icConf = confIn.icache
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen) implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen)
implicit val conf = confIn.copy(dcache = dcConf) implicit val conf = confIn.copy(dcache = dcConf)
require(conf.retireWidth == 1) // for now...
val io = new Bundle { val io = new Bundle {
val tilelink = new TileLinkIO val tilelink = new TileLinkIO

16
rocket/src/main/scala/util.scala
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@ -109,17 +109,21 @@ object Split
} }
// a counter that clock gates most of its MSBs using the LSB carry-out // a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: Bool = Bool(true)) case class WideCounter(width: Int, inc: UInt = UInt(1))
{ {
private val isWide = width >= 4 require(inc.getWidth > 0)
private val smallWidth = if (isWide) log2Up(width) else width private val isWide = width > 2*inc.getWidth
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = Reg(init=UInt(0, smallWidth)) private val small = Reg(init=UInt(0, smallWidth))
private val nextSmall = small + UInt(1, smallWidth+1) private val doInc = inc.orR
when (inc) { small := nextSmall(smallWidth-1,0) } private val nextSmall =
if (inc.getWidth == 1) small + UInt(1, smallWidth+1)
else Cat(UInt(0,1), small) + inc
when (doInc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) { private val large = if (isWide) {
val r = Reg(init=UInt(0, width - smallWidth)) val r = Reg(init=UInt(0, width - smallWidth))
when (inc && nextSmall(smallWidth)) { r := r + UInt(1) } when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) }
r r
} else null } else null