From 0266c1f76a489a9fed0ef5c08199f3fef57a1637 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Fri, 24 Jan 2014 16:36:36 -0800
Subject: [PATCH] Support retirement width > 1 in CSR file

---
 rocket/src/main/scala/dpath_util.scala |  2 +-
 rocket/src/main/scala/tile.scala       |  2 ++
 rocket/src/main/scala/util.scala       | 16 ++++++++++------
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 70e04ec6..08b463b3 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -98,7 +98,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
     val ptbr = UInt(OUTPUT, PADDR_BITS)
     val evec = UInt(OUTPUT, VADDR_BITS+1)
     val exception = Bool(INPUT)
-    val retire = Bool(INPUT)
+    val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
     val cause = UInt(INPUT, conf.xprlen)
     val badvaddr_wen = Bool(INPUT)
     val pc = UInt(INPUT, VADDR_BITS+1)
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 0a4fc7a5..a194fbab 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -7,6 +7,7 @@ import Util._
 case class RocketConfiguration(tl: TileLinkConfiguration,
                                icache: ICacheConfig, dcache: DCacheConfig,
                                fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
+                               retireWidth: Int = 1,
                                vm: Boolean = true,
                                fastLoadWord: Boolean = true,
                                fastLoadByte: Boolean = false,
@@ -30,6 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
   implicit val icConf = confIn.icache
   implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen)
   implicit val conf = confIn.copy(dcache = dcConf)
+  require(conf.retireWidth == 1) // for now...
 
   val io = new Bundle {
     val tilelink = new TileLinkIO
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 09dc7e8b..7735847c 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -109,17 +109,21 @@ object Split
 }
 
 // a counter that clock gates most of its MSBs using the LSB carry-out
-case class WideCounter(width: Int, inc: Bool = Bool(true))
+case class WideCounter(width: Int, inc: UInt = UInt(1))
 {
-  private val isWide = width >= 4
-  private val smallWidth = if (isWide) log2Up(width) else width
+  require(inc.getWidth > 0)
+  private val isWide = width > 2*inc.getWidth
+  private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
   private val small = Reg(init=UInt(0, smallWidth))
-  private val nextSmall = small + UInt(1, smallWidth+1)
-  when (inc) { small := nextSmall(smallWidth-1,0) }
+  private val doInc = inc.orR
+  private val nextSmall =
+    if (inc.getWidth == 1) small + UInt(1, smallWidth+1)
+    else Cat(UInt(0,1), small) + inc
+  when (doInc) { small := nextSmall(smallWidth-1,0) }
 
   private val large = if (isWide) {
     val r = Reg(init=UInt(0, width - smallWidth))
-    when (inc && nextSmall(smallWidth)) { r := r + UInt(1) }
+    when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) }
     r
   } else null