riscv/rocket-chip
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Support retirement width > 1 in CSR file

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This commit is contained in:
Andrew Waterman
2014-01-24 16:36:36 -08:00
parent 267394d3cc
commit 0266c1f76a
3 changed files with 13 additions and 7 deletions
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16
rocket/src/main/scala/util.scala
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@ -109,17 +109,21 @@ object Split
}
// a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: Bool = Bool(true))
case class WideCounter(width: Int, inc: UInt = UInt(1))
{
private val isWide = width >= 4
private val smallWidth = if (isWide) log2Up(width) else width
require(inc.getWidth > 0)
private val isWide = width > 2*inc.getWidth
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = Reg(init=UInt(0, smallWidth))
private val nextSmall = small + UInt(1, smallWidth+1)
when (inc) { small := nextSmall(smallWidth-1,0) }
private val doInc = inc.orR
private val nextSmall =
if (inc.getWidth == 1) small + UInt(1, smallWidth+1)
else Cat(UInt(0,1), small) + inc
when (doInc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) {
val r = Reg(init=UInt(0, width - smallWidth))
when (inc && nextSmall(smallWidth)) { r := r + UInt(1) }
when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) }
r
} else null