riscv/rocket-chip
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Support retirement width > 1 in CSR file

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This commit is contained in:
Andrew Waterman
2014-01-24 16:36:36 -08:00
parent 267394d3cc
commit 0266c1f76a
3 changed files with 13 additions and 7 deletions
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2
rocket/src/main/scala/tile.scala
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@ -7,6 +7,7 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
retireWidth: Int = 1,
vm: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
@ -30,6 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
implicit val icConf = confIn.icache
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen)
implicit val conf = confIn.copy(dcache = dcConf)
require(conf.retireWidth == 1) // for now...
val io = new Bundle {
val tilelink = new TileLinkIO