riscv/rocket-chip
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make Memtest generators more configurable

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This commit is contained in:
Howard Mao 2016-06-06 09:44:09 -07:00
parent 2163ebfca3
commit 022503748e
1 changed files with 6 additions and 5 deletions
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11
groundtest/src/main/scala/generator.scala
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@ -21,9 +21,10 @@ trait HasGeneratorParams {
val genTimeout = 4096 val genTimeout = 4096
val maxRequests = p(MaxGenerateRequests) val maxRequests = p(MaxGenerateRequests)
val startAddress = p(GeneratorStartAddress) val startAddress = p(GeneratorStartAddress)
val genWordBits = p(WordBits) val genWordBits = 32
val genWordBytes = genWordBits / 8 val genWordBytes = genWordBits / 8
val wordOffset = log2Up(genWordBytes) val wordOffset = log2Up(genWordBytes)
val wordSize = MT_WU
require(startAddress % BigInt(genWordBytes) == 0) require(startAddress % BigInt(genWordBytes) == 0)
} }
@ -101,7 +102,7 @@ class UncachedTileLinkGenerator(id: Int)
addr_block = addr_block, addr_block = addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
addr_byte = addr_byte, addr_byte = addr_byte,
operand_size = MT_D, operand_size = wordSize,
alloc = Bool(false)) alloc = Bool(false))
io.mem.acquire.valid := sending && !io.finished io.mem.acquire.valid := sending && !io.finished
@ -157,12 +158,12 @@ class HellaCacheGenerator(id: Int)
} }
} }
val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr) val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr) val req_data = Cat(UInt(id, log2Up(nGens)), req_addr)
io.mem.req.valid := sending && !io.finished io.mem.req.valid := sending && !io.finished
io.mem.req.bits.addr := req_addr io.mem.req.bits.addr := req_addr
io.mem.req.bits.data := req_data io.mem.req.bits.data := req_data
io.mem.req.bits.typ := MT_D io.mem.req.bits.typ := wordSize
io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
io.mem.req.bits.tag := UInt(0) io.mem.req.bits.tag := UInt(0)
@ -176,7 +177,7 @@ class HellaCacheGenerator(id: Int)
io.finished := (state === s_finished) io.finished := (state === s_finished)
assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data || assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
io.mem.resp.bits.data === req_data, io.mem.resp.bits.data(genWordBits - 1, 0) === req_data,
s"Received incorrect data in cached generator ${id}") s"Received incorrect data in cached generator ${id}")
} }