riscv/rocket-chip
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Combine Coreplex and System Module Hierarchies (#875)

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* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
2017-07-23 08:31:04 -07:00
committed by Yunsup Lee
parent f2002839eb
commit 01ca3efc2b
59 changed files with 1536 additions and 1632 deletions
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4
src/main/scala/amba/axi4/Test.scala
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@ -4,7 +4,7 @@ package freechips.rocketchip.amba.axi4
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink.TLError
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.unittest._
@ -98,7 +98,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
val node = AXI4InputNode()
val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)))))
ram.node := TLFragmenter(4, 16)(xbar.node)
error.node := TLFragmenter(4, 16)(xbar.node)