01ca3efc2b
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
140 lines
4.5 KiB
Scala
140 lines
4.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.unittest._
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class RRTest0(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
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new AXI4RegBundle((), _) with RRTest0Bundle)(
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new AXI4RegModule((), _, _) with RRTest0Module)
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class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
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new AXI4RegBundle((), _) with RRTest1Bundle)(
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new AXI4RegModule((), _, _) with RRTest1Module)
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class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
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val xbar = LazyModule(new TLXbar)
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val gpio = LazyModule(new RRTest1(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, true )(TLFragmenter(4, 16)(xbar.node))))
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gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, false)(TLFragmenter(4, 16)(xbar.node))))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4LiteFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new AXI4LiteFuzzRAM(txns)).module)
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io.finished := dut.io.finished
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}
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class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
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val xbar = LazyModule(new TLXbar)
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val gpio = LazyModule(new RRTest0(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,false)(xbar.node)))
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gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,true )(xbar.node)))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4FullFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new AXI4FullFuzzRAM(txns)).module)
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io.finished := dut.io.finished
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}
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trait HasFuzzTarget {
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val fuzzAddr = AddressSet(0x0, 0xfff)
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}
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class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget
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{
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val node = AXI4OutputNode()
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val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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node :=
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AXI4UserYanker()(
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AXI4Deinterleaver(64)(
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TLToAXI4(4)(
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TLDelayer(0.1)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val finished = Bool(OUTPUT)
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}
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io.finished := fuzz.module.io.finished
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}
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}
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class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
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{
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val node = AXI4InputNode()
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val xbar = LazyModule(new TLXbar)
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val ram = LazyModule(new TLRAM(fuzzAddr))
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val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)))))
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ram.node := TLFragmenter(4, 16)(xbar.node)
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error.node := TLFragmenter(4, 16)(xbar.node)
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xbar.node :=
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TLFIFOFixer()(
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TLDelayer(0.1)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4UserYanker(Some(4))(
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AXI4Fragmenter()(
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AXI4IdIndexer(2)(
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node))))))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val master = LazyModule(new AXI4FuzzMaster(txns))
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val slave = LazyModule(new AXI4FuzzSlave)
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slave.node := master.node
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := master.module.io.finished
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}
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}
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class AXI4BridgeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new AXI4FuzzBridge(txns)).module)
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io.finished := dut.io.finished
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}
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