riscv/rocket-chip
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use Wire() correctly to assign a value

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Megan Wachs 2017-04-07 13:58:04 -07:00 committed by Andrew Waterman
parent 9ae4838708
commit 01372e1686
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/uncore/devices/debug/Debug.scala
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@ -788,7 +788,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work.");
flags(cfg.hartSelToHartId(selectedHartReg)).go := goReg
for (component <- 0 until nComponents) {
val componentSel = Wire(component.U)
val componentSel = Wire(init = component.U)
flags(cfg.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)
}