From 01372e1686da0e378a7524a99e49d457361319e8 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 7 Apr 2017 13:58:04 -0700 Subject: [PATCH] use Wire() correctly to assign a value --- src/main/scala/uncore/devices/debug/Debug.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala index bd0c49f8..b7f04b5b 100644 --- a/src/main/scala/uncore/devices/debug/Debug.scala +++ b/src/main/scala/uncore/devices/debug/Debug.scala @@ -788,7 +788,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: "HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work."); flags(cfg.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { - val componentSel = Wire(component.U) + val componentSel = Wire(init = component.U) flags(cfg.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) }