riscv/rocket-chip
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fixes slight bug for non-power of 2 number of ras entries

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This commit is contained in:
Scott Beamer 2015-01-29 15:29:25 -08:00
parent a98127c09e
commit 00e074cdd9
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/btb.scala
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@ -23,7 +23,7 @@ abstract trait BTBParameters extends UsesParameters {
class RAS(nras: Int) { class RAS(nras: Int) {
def push(addr: UInt): Unit = { def push(addr: UInt): Unit = {
when (count < nras) { count := count + 1 } when (count < nras) { count := count + 1 }
val nextPos = Mux(Bool(isPow2(nras)) || pos > 0, pos+1, UInt(0)) val nextPos = Mux(Bool(isPow2(nras)) || pos < nras-1, pos+1, UInt(0))
stack(nextPos) := addr stack(nextPos) := addr
pos := nextPos pos := nextPos
} }