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bram: use new hasti definitions

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This commit is contained in:
Wesley W. Terpstra 2016-05-24 13:26:26 -07:00
parent f138819992
commit 00d31dc5c5
1 changed files with 2 additions and 3 deletions
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5
uncore/src/main/scala/bram.scala
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@ -3,6 +3,7 @@ package uncore
import Chisel._ import Chisel._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import junctions._ import junctions._
import HastiConstants._
class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
with HasTileLinkParameters { with HasTileLinkParameters {
@ -67,8 +68,6 @@ class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) { class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
val io = new HastiSlaveIO val io = new HastiSlaveIO
val hastiDataBytes = hastiDataBits/8
val wdata = Vec.tabulate(hastiDataBytes)(i => io.hwdata(8*(i+1)-1,8*i)) val wdata = Vec.tabulate(hastiDataBytes)(i => io.hwdata(8*(i+1)-1,8*i))
val waddr = Reg(UInt(width = hastiAddrBits)) val waddr = Reg(UInt(width = hastiAddrBits))
val wvalid = Reg(init = Bool(false)) val wvalid = Reg(init = Bool(false))
@ -104,6 +103,6 @@ class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
case ((rbyte, wsel), wbyte) => Mux(wsel && bypass, wbyte, rbyte) case ((rbyte, wsel), wbyte) => Mux(wsel && bypass, wbyte, rbyte)
}.reverse) }.reverse)
io.hreadyout := Bool(true) io.hready := Bool(true)
io.hresp := HRESP_OKAY io.hresp := HRESP_OKAY
} }