riscv/rocket-chip
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Add fclass.{s|d} instructions

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This commit is contained in:
Andrew Waterman 2014-03-10 16:59:07 -07:00
parent ac4b3f9f22
commit 00bc1a2293
3 changed files with 13 additions and 1 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -232,6 +232,8 @@ object FDecode extends DecodeConstants
FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
FCLASS_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCLASS_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),

10
rocket/src/main/scala/fpu.scala
View File

@ -34,6 +34,7 @@ object FPConstants
val FCMD_MIN = Bits("b011000") val FCMD_MIN = Bits("b011000")
val FCMD_MAX = Bits("b011001") val FCMD_MAX = Bits("b011001")
val FCMD_MFTX = Bits("b011100") val FCMD_MFTX = Bits("b011100")
val FCMD_CLASS = Bits("b011101")
val FCMD_MXTF = Bits("b011110") val FCMD_MXTF = Bits("b011110")
val FCMD_MADD = Bits("b100100") val FCMD_MADD = Bits("b100100")
val FCMD_MSUB = Bits("b100101") val FCMD_MSUB = Bits("b100101")
@ -91,6 +92,8 @@ class FPUDecoder extends Module
FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y), FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y),
FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y), FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y),
FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y), FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y),
FCLASS_S -> List(FCMD_CLASS, N,Y,N,N,Y,N,Y,N,N,Y),
FCLASS_D -> List(FCMD_CLASS, N,Y,N,N,N,N,Y,N,N,Y),
FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y), FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y), FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y), FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
@ -203,7 +206,7 @@ class FPToInt extends Module
when (io.in.bits.cmd === FCMD_STORE) { when (io.in.bits.cmd === FCMD_STORE) {
in.in1 := io.in.bits.in2 in.in1 := io.in.bits.in2
}.otherwise { }.otherwise {
val doUpconvert = io.in.bits.single && io.in.bits.cmd != FCMD_MFTX val doUpconvert = io.in.bits.single && io.in.bits.cmd != FCMD_MFTX && io.in.bits.cmd != FCMD_CLASS
in.in1 := Mux(doUpconvert, upconvert(io.in.bits.in1), io.in.bits.in1) in.in1 := Mux(doUpconvert, upconvert(io.in.bits.in1), io.in.bits.in1)
in.in2 := Mux(doUpconvert, upconvert(io.in.bits.in2), io.in.bits.in2) in.in2 := Mux(doUpconvert, upconvert(io.in.bits.in2), io.in.bits.in2)
} }
@ -236,6 +239,11 @@ class FPToInt extends Module
io.out.bits.toint := d2i._1 io.out.bits.toint := d2i._1
io.out.bits.exc := d2i._2 io.out.bits.exc := d2i._2
} }
when (in.cmd === FCMD_CLASS) {
val classify_s = hardfloat.recodedFloatNClassify(in.in1, 23, 9)
val classify_d = hardfloat.recodedFloatNClassify(in.in1, 52, 12)
io.out.bits.toint := Mux(in.single, classify_s, classify_d)
}
when (in.cmd === FCMD_EQ || in.cmd === FCMD_LT || in.cmd === FCMD_LE) { when (in.cmd === FCMD_EQ || in.cmd === FCMD_LT || in.cmd === FCMD_LE) {
io.out.bits.toint := dcmp_out io.out.bits.toint := dcmp_out
io.out.bits.exc := dcmp_exc io.out.bits.exc := dcmp_exc

2
rocket/src/main/scala/instructions.scala
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@ -146,6 +146,8 @@ object Instructions {
def FMAX_D = Bits("b1100101??????????000?????1010011") def FMAX_D = Bits("b1100101??????????000?????1010011")
def FMV_X_S = Bits("b111000000000?????000?????1010011") def FMV_X_S = Bits("b111000000000?????000?????1010011")
def FMV_X_D = Bits("b111000100000?????000?????1010011") def FMV_X_D = Bits("b111000100000?????000?????1010011")
def FCLASS_S = Bits("b111010000000?????000?????1010011")
def FCLASS_D = Bits("b111010100000?????000?????1010011")
def FMV_S_X = Bits("b111100000000?????000?????1010011") def FMV_S_X = Bits("b111100000000?????000?????1010011")
def FMV_D_X = Bits("b111100100000?????000?????1010011") def FMV_D_X = Bits("b111100100000?????000?????1010011")
def FLW = Bits("b?????????????????010?????0000111") def FLW = Bits("b?????????????????010?????0000111")