riscv/rocket-chip
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cleanup pending signals

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This commit is contained in:
Henry Cook 2015-03-18 22:14:41 -07:00
parent 002851f836
commit 004ad11af6
2 changed files with 15 additions and 22 deletions
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21
uncore/src/main/scala/cache.scala
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@ -606,9 +606,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val xact_meta = Reg{ new L2Metadata } val xact_meta = Reg{ new L2Metadata }
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val pending_coh = Reg{ xact_meta.coh.clone } val pending_coh = Reg{ xact_meta.coh.clone }
val present_puts = Reg(init=Bits(0, width = innerDataBeats)) val pending_puts = Reg(init=Bits(0, width = innerDataBeats))
present_puts := (present_puts | addPendingBitWhenHasData(io.inner.acquire)) pending_puts := (pending_puts & dropPendingBitWhenHasData(io.inner.acquire))
val needs_more_put_data = !present_puts.andR val needs_more_put_data = pending_puts.orR
val do_allocate = xact.allocate() val do_allocate = xact.allocate()
val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1))) val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
@ -648,9 +648,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val pending_reads = Reg(init=Bits(0, width = innerDataBeats)) val pending_reads = Reg(init=Bits(0, width = innerDataBeats))
pending_reads := (pending_reads | pending_reads := (pending_reads |
addPendingBitWhenWmaskIsNotFull(io.inner.acquire)) & addPendingBitWhenGetOrAtomic(io.inner.acquire)) &
(dropPendingBit(io.data.read) & (dropPendingBit(io.data.read) &
dropPendingBitWhenWmaskIsFull(io.inner.acquire) &
dropPendingBitWhenHasData(io.inner.release) & dropPendingBitWhenHasData(io.inner.release) &
dropPendingBitWhenHasData(io.outer.grant)) dropPendingBitWhenHasData(io.outer.grant))
val curr_read_beat = PriorityEncoder(pending_reads) val curr_read_beat = PriorityEncoder(pending_reads)
@ -824,14 +823,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
xact := io.iacq() xact := io.iacq()
xact.data := UInt(0) xact.data := UInt(0)
wmask_buffer.foreach { w => w := UInt(0) } wmask_buffer.foreach { w => w := UInt(0) }
present_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType), pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
addPendingBitWhenHasData(io.inner.acquire), dropPendingBitWhenHasData(io.inner.acquire),
UInt(0))
pending_reads := Mux(io.iacq().isBuiltInType(),
addPendingBitWhenGetOrAtomic(io.inner.acquire),
SInt(-1, width = innerDataBeats)).toUInt SInt(-1, width = innerDataBeats)).toUInt
pending_reads := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
UInt(0),
Mux(io.iacq().isSubBlockType(),
addPendingBitWhenWmaskIsNotFull(io.inner.acquire),
SInt(-1, width = innerDataBeats)).toUInt)
pending_writes := addPendingBitWhenHasData(io.inner.acquire) pending_writes := addPendingBitWhenHasData(io.inner.acquire)
pending_resps := UInt(0) pending_resps := UInt(0)
pending_ignt_data := UInt(0) pending_ignt_data := UInt(0)

14
uncore/src/main/scala/uncore.scala
View File

@ -160,14 +160,10 @@ abstract class XactTracker extends CoherenceAgentModule {
~UIntToOH(in.bits.payload.addr_beat) ~UIntToOH(in.bits.payload.addr_beat)
} }
//TODO | with existing wmask_buffer? def addPendingBitWhenGetOrAtomic(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
def addPendingBitWhenWmaskIsNotFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = { val a = in.bits.payload
Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) & Fill(a.tlDataBeats, in.fire() && a.isBuiltInType() &&
UIntToOH(in.bits.payload.addr_beat) (a.is(Acquire.getType) || a.is(Acquire.getBlockType) || a.is(Acquire.putAtomicType))) &
} UIntToOH(a.addr_beat)
def dropPendingBitWhenWmaskIsFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
~Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.wmask().andR) |
~UIntToOH(in.bits.payload.addr_beat)
} }
} }