riscv/rocket-chip
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cleanup pending signals

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This commit is contained in:
Henry Cook
2015-03-18 22:14:41 -07:00
parent 002851f836
commit 004ad11af6
2 changed files with 15 additions and 22 deletions
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14
uncore/src/main/scala/uncore.scala
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@ -160,14 +160,10 @@ abstract class XactTracker extends CoherenceAgentModule {
~UIntToOH(in.bits.payload.addr_beat)
}
//TODO | with existing wmask_buffer?
def addPendingBitWhenWmaskIsNotFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) &
UIntToOH(in.bits.payload.addr_beat)
}
def dropPendingBitWhenWmaskIsFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
~Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.wmask().andR) |
~UIntToOH(in.bits.payload.addr_beat)
def addPendingBitWhenGetOrAtomic(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
val a = in.bits.payload
Fill(a.tlDataBeats, in.fire() && a.isBuiltInType() &&
(a.is(Acquire.getType) || a.is(Acquire.getBlockType) || a.is(Acquire.putAtomicType))) &
UIntToOH(a.addr_beat)
}
}