rocket-chip/bootrom/bootrom.S

#define DRAM_BASE 0x80000000

.section .text.start, "ax", @progbits
.globl _start
_start:
  li s0, DRAM_BASE
  csrr a0, mhartid
  la a1, _dtb
  jr s0

.section .text.hang, "ax", @progbits
.globl _hang
_hang:
  csrr a0, mhartid
  la a1, _dtb
1:
  wfi
  j 1b

.section .rodata.dtb, "a", @progbits
.globl _dtb
.align 5, 0
_dtb:
.ascii "DTB goes here"
bootrom: also setup SBI a0+a1 for when we hang (#617) This way a program started by the debugger still has the DTB handy. 2017-03-27 09:01:05 +02:00			`#define DRAM_BASE 0x80000000`

bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 23:55:57 +01:00			`.section .text.start, "ax", @progbits`
			`.globl _start`
generate BootROM contents from assembly code 2016-08-05 20:07:42 +02:00			`_start:`
bootrom: also setup SBI a0+a1 for when we hang (#617) This way a program started by the debugger still has the DTB handy. 2017-03-27 09:01:05 +02:00			`li s0, DRAM_BASE`
bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 23:55:57 +01:00			`csrr a0, mhartid`
			`la a1, _dtb`
			`jr s0`

			`.section .text.hang, "ax", @progbits`
			`.globl _hang`
			`_hang:`
bootrom: also setup SBI a0+a1 for when we hang (#617) This way a program started by the debugger still has the DTB handy. 2017-03-27 09:01:05 +02:00			`csrr a0, mhartid`
			`la a1, _dtb`
			`1:`
bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 23:55:57 +01:00			`wfi`
bootrom: also setup SBI a0+a1 for when we hang (#617) This way a program started by the debugger still has the DTB handy. 2017-03-27 09:01:05 +02:00			`j 1b`
bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 23:55:57 +01:00
			`.section .rodata.dtb, "a", @progbits`
			`.globl _dtb`
			`.align 5, 0`
			`_dtb:`
			`.ascii "DTB goes here"`