2017-02-09 22:59:09 +01:00
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// See LICENSE.SiFive for license details.
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.tile
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2017-02-09 22:59:09 +01:00
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import Chisel._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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2017-02-09 22:59:09 +01:00
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case object SharedMemoryTLEdge extends Field[TLEdgeOut]
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case object TileKey extends Field[TileParams]
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2017-04-28 00:22:52 +02:00
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case object ResetVectorBits extends Field[Int]
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case object MaxHartIdBits extends Field[Int]
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2017-02-09 22:59:09 +01:00
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trait TileParams {
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val core: CoreParams
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val icache: Option[ICacheParams]
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val dcache: Option[DCacheParams]
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val rocc: Seq[RoCCParams]
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val btb: Option[BTBParams]
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}
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trait HasTileParameters {
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implicit val p: Parameters
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val tileParams: TileParams = p(TileKey)
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val usingVM = tileParams.core.useVM
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val usingUser = tileParams.core.useUser || usingVM
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val usingDebug = tileParams.core.useDebug
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val usingRoCC = !tileParams.rocc.isEmpty
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val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
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val usingPTW = usingVM
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2017-03-07 06:35:45 +01:00
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val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
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2017-04-28 00:22:52 +02:00
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val hartIdLen = p(MaxHartIdBits)
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2017-02-09 22:59:09 +01:00
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def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
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}
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abstract class BareTile(implicit p: Parameters) extends LazyModule
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abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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2017-04-28 00:22:52 +02:00
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/** Uses TileLink master port to connect caches and accelerators to the coreplex */
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trait HasTileLinkMasterPort {
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2017-02-09 22:59:09 +01:00
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implicit val p: Parameters
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val module: HasTileLinkMasterPortModule
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val masterNode = TLOutputNode()
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2017-05-17 01:12:01 +02:00
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val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
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masterNode := tileBus.node
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2017-02-09 22:59:09 +01:00
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}
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trait HasTileLinkMasterPortBundle {
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val outer: HasTileLinkMasterPort
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val master = outer.masterNode.bundleOut
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}
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trait HasTileLinkMasterPortModule {
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val outer: HasTileLinkMasterPort
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val io: HasTileLinkMasterPortBundle
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}
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2017-04-28 00:22:52 +02:00
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/** Some other standard inputs */
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trait HasExternallyDrivenTileConstants extends Bundle {
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implicit val p: Parameters
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val hartid = UInt(INPUT, p(MaxHartIdBits))
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val resetVector = UInt(INPUT, p(ResetVectorBits))
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}
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/** Base class for all Tiles that use TileLink */
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2017-02-09 22:59:09 +01:00
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abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
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2017-07-07 19:48:16 +02:00
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with HasTileParameters
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with HasTileLinkMasterPort {
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2017-02-09 22:59:09 +01:00
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override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
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}
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class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
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2017-03-30 04:14:04 +02:00
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with HasTileLinkMasterPortBundle
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2017-04-28 00:22:52 +02:00
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with HasExternallyDrivenTileConstants
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2017-02-09 22:59:09 +01:00
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class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
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with HasTileLinkMasterPortModule
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