500 lines
14 KiB
Scala
500 lines
14 KiB
Scala
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// Generate memory traces that result from random sequences of memory
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// operations. These traces can then be validated by an external
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// tool. A trace is a simply sequence of memory requests and
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// responses.
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package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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// ==========================
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// Trace-generator parameters
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// ==========================
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// Compile-time parameters:
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//
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// * The id of the generator (there may be more than one in a
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// multi-core system).
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//
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// * The total number of generators present in the system.
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//
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// * The desired number of requests to be sent by each generator.
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//
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// * A list of physical addresses from which an address is drawn when
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// generating a fresh request.
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case object NumGens extends Field[Int]
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case object NumReqsPerGen extends Field[Int]
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case object AddressBag extends Field[List[Int]]
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trait HasTraceGenParams {
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implicit val p: Parameters
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val numGens = p(NumGens)
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val numBitsInId = log2Up(numGens)
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val numReqsPerGen = p(NumReqsPerGen)
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val memRespTimeout = 4096
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val numBitsInWord = p(WordBits)
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val numBytesInWord = numBitsInWord / 8
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val numBitsInWordOffset = log2Up(numBytesInWord)
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val addressBag = p(AddressBag)
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val logNumAddrsInTrace = log2Up(addressBag.length)
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require(numBytesInWord * 8 == numBitsInWord)
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require(1 << logNumAddrsInTrace == addressBag.length)
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}
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// ============
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// Trace format
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// ============
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// Let <id> denote a generator id;
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// <addr> denote an address (in hex);
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// <data> denote a value that is stored at an address;
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// <tag> denote a unique request/response id;
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// and <time> denote an integer representing a cycle-count.
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// Each line in the trace takes one of the following formats.
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//
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// <id>: load-req <addr> #<tag> @<time>
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// <id>: load-reserve-req <addr> #<tag> @<time>
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// <id>: store-req <data> <addr> #<tag> @<time>
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// <id>: store-cond-req <data> <addr> #<tag> @<time>
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// <id>: swap-req <data> <addr> #<tag> @<time>
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// <id>: resp <data> #<tag> @<time>
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// <id>: fence-req @<time>
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// <id>: fence-resp @<time>
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// NOTE: The (address, value) pair of every generated store is unique,
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// i.e. the same value is never written to the same address twice.
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// This aids trace validation.
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// ============
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// Random seeds
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// ============
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// The generator employs "unitialised registers" to seed its PRNGs;
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// these are randomly initialised by the C++ backend. This means that
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// the "-s" command-line argument to the Rocket emulator can be used
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// to generate new traces, or to replay specific ones.
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// ===========
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// Tag manager
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// ===========
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// This is used to obtain unique tags for memory requests: each
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// request must carry a unique tag since responses can come back
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// out-of-order.
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//
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// The tag manager can be viewed as a set of tags. The user can take
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// a tag out of the set (if there is one available) and later put it
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// back.
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class TagMan(val logNumTags : Int) extends Module {
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val io = new Bundle {
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// Is there a tag available?
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val available = Bool(OUTPUT)
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// If so, which one?
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val tagOut = UInt(OUTPUT, logNumTags)
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// User pulses this to take the currently available tag
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val take = Bool(INPUT)
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// User pulses this to put a tag back
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val put = Bool(INPUT)
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// And the tag put back is
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val tagIn = UInt(INPUT, logNumTags)
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}
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// Total number of tags available
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val numTags = 1 << logNumTags
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// For each tag, record whether or not it is in use
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val inUse = List.fill(numTags)(Reg(init = Bool(false)))
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// Mapping from each tag to its 'inUse' bit
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val inUseMap = (0 to numTags-1).map(i => UInt(i, logNumTags)).zip(inUse)
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// Next tag to offer
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val nextTag = Reg(init = UInt(0, logNumTags))
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io.tagOut := nextTag
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// Is the next tag available?
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io.available := ~Lookup(nextTag, Bool(true), inUseMap)
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// When user takes a tag
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when (io.take) {
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for ((i, b) <- inUseMap) {
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when (i === nextTag) { b := Bool(true) }
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}
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nextTag := nextTag + UInt(1)
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}
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// When user puts a tag back
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when (io.put) {
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for ((i, b) <- inUseMap) {
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when (i === io.tagIn) { b := Bool(false) }
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}
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}
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}
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// ===============
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// Trace generator
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// ===============
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class TraceGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p)
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with HasTraceGenParams {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new HellaCacheIO
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}
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// Random addresses
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// ----------------
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// Address list taken from module parameters.
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val numAddrsInTrace = 1 << logNumAddrsInTrace
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val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))
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// A random index into the address bag.
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val randAddrIndex = Module(new LCG(logNumAddrsInTrace)).io.out
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// A random address from the address bag.
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val addrIndices = (0 to numAddrsInTrace-1).
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map(i => UInt(i, logNumAddrsInTrace))
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val randAddr = MuxLookup(randAddrIndex, UInt(0),
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addrIndices.zip(bagOfAddrs))
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// Random opcodes
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// --------------
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// Generate random opcodes for memory operations according to the
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// given frequency distribution.
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// Opcodes
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val (opNop :: opLoad :: opStore ::
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opFence :: opLRSC :: opSwap ::
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opDelay :: Nil) = Enum(Bits(), 7)
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// Distribution specified as a list of (frequency,value) pairs.
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// NOTE: frequencies must sum to a power of two.
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//val randOp = Frequency(List(
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// (10, opLoad),
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// (10, opStore),
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// (4, opFence),
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// (3, opLRSC),
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// (3, opSwap),
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// (2, opDelay)))
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// For now, just generate loads and stores as this is enough to
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// expose strange behaviour.
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val randOp = Frequency(List(
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(15, opLoad),
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(15, opStore),
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(2, opDelay)))
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// Request/response tags
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// ---------------------
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// Responses may come back out-of-order. Each request and response
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// therefore contains a unique 7-bit identifier, referred to as a
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// "tag", used to match each response with its corresponding request.
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// Create a tag manager giving out unique 3-bit tags
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val tagMan = Module(new TagMan(3))
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// Default inputs
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tagMan.io.take := Bool(false);
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tagMan.io.put := Bool(false);
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tagMan.io.tagIn := UInt(0);
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// Cycle counter
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// -------------
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// 32-bit cycle count used to record send-times of requests and
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// receive-times of respones.
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val cycleCount = Reg(init = UInt(0, 32))
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cycleCount := cycleCount + UInt(1);
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// Delay timer
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// -----------
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// Used to implement the delay operation and to insert random
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// delays between load-reserve and store-conditional commands.
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// A 16-bit timer is plenty
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val delayTimer = Module(new DynamicTimer(16))
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// Used to generate a random delay period
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val randDelayBase = Module(new LCG16()).io.out
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// Random delay period: usually small, occasionally big
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val randDelay = Frequency(List(
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(14, UInt(0, 13) ## randDelayBase(2, 0)),
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(2, UInt(0, 11) ## randDelayBase(5, 0))))
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// Default inputs
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delayTimer.io.start := Bool(false)
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delayTimer.io.period := randDelay
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delayTimer.io.stop := Bool(false)
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// Operation dispatch
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// ------------------
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// Hardware thread id
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val tid = UInt(id, numBitsInId)
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// Request & response count
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val reqCount = Reg(init = UInt(0, 32))
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val respCount = Reg(init = UInt(0, 32))
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// Current operation being executed
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val currentOp = Reg(init = opNop)
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// If larger than 0, a multi-cycle operation is in progress.
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// Value indicates stage of progress.
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val opInProgress = Reg(init = UInt(0, 2))
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// Indicate when a fresh request is to be sent
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val sendFreshReq = Wire(Bool())
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sendFreshReq := Bool(false)
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// Used to generate unique data values
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val nextData = Reg(init = UInt(1, numBitsInWord-numBitsInId))
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// Registers for all the interesting parts of a request
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val reqValid = Reg(init = Bool(false))
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val reqAddr = Reg(init = UInt(0, numBitsInWord))
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val reqData = Reg(init = UInt(0, numBitsInWord))
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val reqCmd = Reg(init = UInt(0, 5))
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val reqTag = Reg(init = UInt(0, 7))
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// Condition on being allowed to send a fresh request
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val canSendFreshReq = (!reqValid || io.mem.req.fire()) &&
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tagMan.io.available
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// Operation dispatch
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when (reqCount < UInt(numReqsPerGen)) {
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// No-op
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when (currentOp === opNop) {
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// Move on to a new operation
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currentOp := randOp
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}
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// Fence
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when (currentOp === opFence) {
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when (opInProgress === UInt(0) && !reqValid) {
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// Emit fence request
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printf("%d: fence-req @%d\n", tid, cycleCount)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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// Wait until all requests have had a response
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.elsewhen (io.mem.ordered && reqCount === respCount) {
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// Emit fence response
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printf("%d: fence-resp @%d\n", tid, cycleCount)
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// Move on to a new operation
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currentOp := randOp
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// Operation finished
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opInProgress := UInt(0)
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}
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}
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// Delay
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when (currentOp === opDelay) {
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when (opInProgress === UInt(0)) {
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// Start timer
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delayTimer.io.start := Bool(true)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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.elsewhen (delayTimer.io.timeout) {
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// Move on to a new operation
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currentOp := randOp
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// Operation finished
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opInProgress := UInt(0)
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}
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}
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// Load, store, or atomic swap
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when (currentOp === opLoad ||
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currentOp === opStore ||
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currentOp === opSwap) {
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when (canSendFreshReq) {
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// Set address
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reqAddr := randAddr
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// Set command
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when (currentOp === opLoad) {
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reqCmd := M_XRD
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} .elsewhen (currentOp === opStore) {
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reqCmd := M_XWR
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} .elsewhen (currentOp === opSwap) {
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reqCmd := M_XA_SWAP
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}
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// Send request
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sendFreshReq := Bool(true)
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// Move on to a new operation
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currentOp := randOp
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}
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}
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// Load-reserve and store-conditional
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// First issue an LR, then delay, then issue an SC
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when (currentOp === opLRSC) {
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// LR request has not yet been sent
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when (opInProgress === UInt(0)) {
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when (canSendFreshReq) {
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// Set address and command
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reqAddr := randAddr
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reqCmd := M_XLR
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// Send request
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sendFreshReq := Bool(true)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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}
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// LR request has been sent, start delay timer
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when (opInProgress === UInt(1)) {
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// Start timer
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delayTimer.io.start := Bool(true)
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// Indicate that delay has started
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opInProgress := UInt(2)
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}
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// Delay in progress
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when (opInProgress === UInt(2)) {
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when (delayTimer.io.timeout) {
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// Delay finished
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opInProgress := UInt(3)
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}
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}
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// Delay finished, send SC request
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when (opInProgress === UInt(3)) {
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when (canSendFreshReq) {
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// Set command, but leave address
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// i.e. use same address as LR did
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reqCmd := M_XSC
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// Send request
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sendFreshReq := Bool(true)
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// Multi-cycle operation finished
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opInProgress := UInt(0)
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// Move on to a new operation
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currentOp := randOp
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}
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}
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}
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}
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// Sending of requests
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// -------------------
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when (sendFreshReq) {
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// Grab a unique tag for the request
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reqTag := Cat(UInt(0), tagMan.io.tagOut)
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tagMan.io.take := Bool(true)
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// Fill in unique data
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reqData := Cat(nextData, tid)
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nextData := nextData + UInt(1)
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// Request is good to go!
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reqValid := Bool(true)
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// Increment request count
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reqCount := reqCount + UInt(1)
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}
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.elsewhen (io.mem.req.fire()) {
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// Request has been sent and there is no new request ready
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reqValid := Bool(false)
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}
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// Wire up interface to memory
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io.mem.req.valid := reqValid
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io.mem.req.bits.addr := reqAddr
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io.mem.req.bits.data := reqData
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.cmd := reqCmd
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io.mem.req.bits.tag := reqTag
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io.mem.req.bits.kill := Bool(false)
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io.mem.req.bits.phys := Bool(true)
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// On cycle when request is actually sent, print it
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when (io.mem.req.fire()) {
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// Short-hand for address
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val addr = io.mem.req.bits.addr
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// Print thread id
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printf("%d:", tid)
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// Print command
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when (reqCmd === M_XRD) {
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printf(" load-req 0x%x", addr)
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}
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when (reqCmd === M_XLR) {
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printf(" load-reserve-req 0x%x", addr)
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}
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when (reqCmd === M_XWR) {
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printf(" store-req %d 0x%x", reqData, addr)
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}
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when (reqCmd === M_XSC) {
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printf(" store-cond-req %d 0x%x", reqData, addr)
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}
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when (reqCmd === M_XA_SWAP) {
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printf(" swap-req %d 0x%x", reqData, addr)
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}
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// Print tag
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printf(" #%d", reqTag)
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// Print time
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printf(" @%d\n", cycleCount)
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|
}
|
||
|
|
||
|
// Handling of responses
|
||
|
// ---------------------
|
||
|
|
||
|
// When a response is received
|
||
|
when (io.mem.resp.valid) {
|
||
|
// Put tag back in tag set
|
||
|
tagMan.io.tagIn := io.mem.resp.bits.tag
|
||
|
tagMan.io.put := Bool(true)
|
||
|
// Print response
|
||
|
printf("%d: resp %d #%d @%d\n", tid,
|
||
|
io.mem.resp.bits.data, io.mem.resp.bits.tag, cycleCount)
|
||
|
// Increment response count
|
||
|
respCount := respCount + UInt(1)
|
||
|
}
|
||
|
|
||
|
// Response timeouts
|
||
|
// -----------------
|
||
|
//
|
||
|
// Raise an error if a response takes too long to come back.
|
||
|
|
||
|
val timeout = Timer(memRespTimeout, io.mem.req.fire(), io.mem.resp.valid)
|
||
|
assert(!timeout, s"Trace generator ${id} timed out waiting for response")
|
||
|
|
||
|
// Termination condition
|
||
|
// ---------------------
|
||
|
|
||
|
io.finished := reqCount === UInt(numReqsPerGen) &&
|
||
|
respCount === UInt(numReqsPerGen)
|
||
|
}
|
||
|
|
||
|
// =======================
|
||
|
// Trace-generator wrapper
|
||
|
// =======================
|
||
|
|
||
|
class GroundTestTraceGenerator(id: Int)(implicit p: Parameters)
|
||
|
extends GroundTest()(p) with HasTraceGenParams {
|
||
|
|
||
|
disablePorts(cache = false)
|
||
|
|
||
|
val traceGen = Module(new TraceGenerator(id))
|
||
|
io.cache <> traceGen.io.mem
|
||
|
|
||
|
io.finished := traceGen.io.finished
|
||
|
}
|