31 lines
1.1 KiB
Scala
31 lines
1.1 KiB
Scala
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package uncore
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import Chisel._
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import junctions._
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import cde.{Parameters, Field}
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class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
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val io = new NastiIO().flip
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val ar = Queue(io.ar, 1)
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// This assumes ROMs are in read-only parts of the address map.
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// Reuse b_queue code from NastiErrorSlave if this assumption is bad.
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when (ar.valid) { assert(ar.bits.len === UInt(0), "Can't burst-read from NastiROM") }
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assert(!(io.aw.valid || io.w.valid), "Can't write to NastiROM")
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io.aw.ready := Bool(false)
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io.w.ready := Bool(false)
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io.b.valid := Bool(false)
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val byteWidth = io.r.bits.nastiXDataBits / 8
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val rows = (contents.size + byteWidth - 1)/byteWidth + 1
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val rom = Vec.tabulate(rows) { i =>
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val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) })
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}
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val rdata_word = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
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val rdata = new LoadGen(Cat(UInt(1), ar.bits.size), ar.bits.addr, rdata_word, Bool(false), byteWidth).data
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io.r <> ar
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io.r.bits := NastiReadDataChannel(ar.bits.id, rdata)
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}
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