2016-05-03 00:19:43 +02:00
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// See LICENSE for license details.
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package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import junctions.NastiConstants._
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import cde.{Parameters, Field}
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/** Number of tiles */
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case object NTiles extends Field[Int]
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2016-06-06 08:47:56 +02:00
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class PRCIInterrupts extends Bundle {
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val mtip = Bool()
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val meip = Bool()
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val seip = Bool()
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val debug = Bool()
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}
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2016-05-03 02:49:10 +02:00
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class PRCITileIO(implicit p: Parameters) extends Bundle {
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2016-05-03 00:19:43 +02:00
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val reset = Bool(OUTPUT)
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val id = UInt(OUTPUT, log2Up(p(NTiles)))
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2016-06-06 08:47:56 +02:00
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val interrupts = new PRCIInterrupts {
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2016-05-03 00:19:43 +02:00
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val msip = Bool()
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}.asOutput
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2016-05-03 02:49:10 +02:00
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override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
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}
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2016-06-06 08:06:21 +02:00
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/** Power, Reset, Clock, Interrupt */
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2016-05-03 02:49:10 +02:00
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class PRCI(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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2016-06-06 08:47:56 +02:00
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val interrupts = Vec(p(NTiles), new PRCIInterrupts).asInput
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2016-05-03 02:49:10 +02:00
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val tl = new ClientUncachedTileLinkIO().flip
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2016-06-06 08:06:21 +02:00
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val tiles = Vec(p(NTiles), new PRCITileIO)
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2016-05-03 02:49:10 +02:00
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}
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2016-06-06 08:06:21 +02:00
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val ipi = Reg(init=Vec.fill(p(NTiles))(Bool(false)))
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2016-05-03 02:49:10 +02:00
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val acq = Queue(io.tl.acquire, 1)
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2016-06-06 08:06:21 +02:00
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val addr = acq.bits.full_addr()
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2016-05-03 02:49:10 +02:00
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val read = acq.bits.isBuiltInType(Acquire.getType)
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val write = acq.bits.isBuiltInType(Acquire.putType)
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2016-06-06 08:06:21 +02:00
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val rdata = Wire(init=UInt(0))
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val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
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2016-05-03 02:49:10 +02:00
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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2016-06-06 08:06:21 +02:00
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when (write) {
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val ipiRegBytes = 4
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val regsPerBeat = tlDataBytes/ipiRegBytes
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val word =
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if (regsPerBeat >= ipi.size) UInt(0)
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else addr(log2Up(ipi.size*ipiRegBytes)-1,log2Up(tlDataBytes))
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for (i <- 0 until ipi.size by regsPerBeat) {
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when (word === i/regsPerBeat) {
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rdata := Cat(ipi.slice(i, i + regsPerBeat).map(p => Cat(UInt(0, 8*ipiRegBytes-1), p)).reverse)
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for (j <- 0 until (regsPerBeat min (ipi.size - i))) {
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when (write) { ipi(i+j) := masked_wdata(j*8*ipiRegBytes) }
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}
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}
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}
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2016-05-03 02:49:10 +02:00
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}
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2016-06-06 08:06:21 +02:00
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for ((tile, i) <- io.tiles zipWithIndex) {
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tile.interrupts := io.interrupts(i)
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tile.interrupts.msip := ipi(i)
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tile.id := UInt(i)
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}
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2016-05-03 00:19:43 +02:00
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}
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