294 lines
9.1 KiB
Coq
294 lines
9.1 KiB
Coq
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// See LICENSE for license details.
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extern "A" void memory_tick
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(
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input reg [31:0] channel,
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input reg ar_valid,
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output reg ar_ready,
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input reg [`MEM_ADDR_BITS-1:0] ar_addr,
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input reg [`MEM_ID_BITS-1:0] ar_id,
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input reg [2:0] ar_size,
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input reg [7:0] ar_len,
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input reg aw_valid,
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output reg aw_ready,
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input reg [`MEM_ADDR_BITS-1:0] aw_addr,
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input reg [`MEM_ID_BITS-1:0] aw_id,
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input reg [2:0] aw_size,
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input reg [7:0] aw_len,
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input reg w_valid,
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output reg w_ready,
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input reg [`MEM_STRB_BITS-1:0] w_strb,
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input reg [`MEM_DATA_BITS-1:0] w_data,
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input reg w_last,
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output reg r_valid,
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input reg r_ready,
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output reg [1:0] r_resp,
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output reg [`MEM_ID_BITS-1:0] r_id,
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output reg [`MEM_DATA_BITS-1:0] r_data,
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output reg r_last,
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output reg b_valid,
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input reg b_ready,
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output reg [1:0] b_resp,
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output reg [`MEM_ID_BITS-1:0] b_id
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);
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module rocketDTMTestHarness;
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reg [31:0] seed;
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initial seed = $get_initial_random_seed();
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//-----------------------------------------------
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// Instantiate the processor
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reg clk = 1'b0;
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reg reset = 1'b1;
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reg r_reset = 1'b1;
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reg start = 1'b0;
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always #`CLOCK_PERIOD clk = ~clk;
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reg [ 31:0] n_mem_channel = `N_MEM_CHANNELS;
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reg [ 31:0] mem_width = `MEM_DATA_BITS;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [1023:0] vcdfile = 0;
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reg verbose = 0;
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wire printf_cond = verbose && !reset;
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integer stderr = 32'h80000002;
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`include `TBVFRAG
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always @(posedge clk)
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begin
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r_reset <= reset;
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end
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reg [31:0] exit = 0;
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//-----------------------------------------------
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// Instantiate DTM and Synchronizers
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// JTAG Interface
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wire debug_TDI;
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wire debug_TDO;
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wire debug_TCK;
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wire debug_TMS;
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wire debug_TRST;
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wire debug_DRV_TDO;
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//=================================================
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// JTAG VPI Server
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wire cheater_TCK;
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jtag_vpi #(
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.DEBUG_INFO(0),
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//parameter TP = 1,
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.TCK_HALF_PERIOD(5),
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.CMD_DELAY(10)
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) // Clock half period (Clock period = 10 ns => 100 MHz)
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jtag_vpi (
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.tms(debug_TMS),
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.tck(debug_TCK),
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.tdi(debug_TDI),
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.tdo(debug_TDO),
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.enable(~reset),
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.init_done(~reset)
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);
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//=================================================
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// DTM <-> Synchronizers Interface
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localparam DEBUG_ADDR_BITS = 5;
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localparam DEBUG_DATA_BITS = 34;
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localparam DEBUG_OP_BITS = 2;
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wire dtm_req_ready;
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wire dtm_req_valid;
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wire [DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS - 1 : 0 ] dtm_req_data;
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wire dtm_resp_ready;
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wire dtm_resp_valid;
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wire [DEBUG_OP_BITS + DEBUG_DATA_BITS - 1 :0 ] dtm_resp_data;
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DebugTransportModuleJtag #(.DEBUG_OP_BITS(DEBUG_OP_BITS),
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.DEBUG_ADDR_BITS(DEBUG_ADDR_BITS),
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.DEBUG_DATA_BITS(DEBUG_DATA_BITS)
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) debugTransportModuleJtag0 (
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//JTAG Interface
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.TDI(debug_TDI),
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.TDO(debug_TDO),
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.TCK(debug_TCK),
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.TMS(debug_TMS),
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.TRST(debug_TRST),
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.DRV_TDO(debug_DRV_TDO),
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.dtm_req_ready(dtm_req_ready),
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.dtm_req_valid(dtm_req_valid),
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.dtm_req_data(dtm_req_data),
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.dtm_resp_ready(dtm_resp_ready),
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.dtm_resp_valid(dtm_resp_valid),
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.dtm_resp_data(dtm_resp_data)
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);
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`ifdef VERILOG_DEBUG_SYNC
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AsyncFifo #(.DEPTH_LG_2(0),
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.WIDTH(DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS))
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debugBusReqFifo(
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// Write Interface
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.clk_w(~debug_TCK),
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.reset_w(debug_TRST),
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.ready_w(dtm_req_ready),
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.valid_w(dtm_req_valid),
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.data_w(dtm_req_data),
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.clk_r(clk),
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.reset_r(reset),
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.ready_r(debug_req_ready),
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.valid_r(debug_req_valid),
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.data_r({debug_req_bits_addr, debug_req_bits_data, debug_req_bits_op})
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);
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AsyncFifo #(.DEPTH_LG_2(0),
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.WIDTH(DEBUG_OP_BITS + DEBUG_DATA_BITS))
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debugBusRespFifo(
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.clk_w(clk),
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.reset_w(reset),
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.ready_w(debug_resp_ready),
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.valid_w(debug_resp_valid),
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.data_w({debug_resp_bits_data, debug_resp_bits_resp}),
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.clk_r(debug_TCK),
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.reset_r(debug_TRST),
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.ready_r(dtm_resp_ready),
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.valid_r(dtm_resp_valid),
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.data_r(dtm_resp_data)
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);
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// This is cheating / potentially incorrect!!! It needs to be more
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// clearly specified as to what the behavior of TRST is.
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assign debug_TRST = reset;
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// The TCK cheat is not needed for this side of the ifdef
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// because both DTM and synchronizer
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// logic is asynchronously reset as needed.
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`else // !`ifdef VERILOG_DEBUG_SYNC
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// This is cheating / potentially incorrect!!! It needs to be more
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// clearly specified as to what the behavior of TRST is.
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assign debug_TRST = reset;
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// This is TOTAL cheating!!! The synchronizer
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// logic should be asynchronously reset, or we should
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// specify the TCK/TRST requirements for a synchronous reset.
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assign debug_clk = reset ? clk : debug_TCK;
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assign debug_reset = debug_TRST;
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assign debug_req_valid = dtm_req_valid;
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assign {debug_req_bits_addr, debug_req_bits_data, debug_req_bits_op} = dtm_req_data;
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assign dtm_req_ready = debug_req_ready;
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assign dtm_resp_valid = debug_resp_valid;
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assign dtm_resp_data = {debug_resp_bits_data, debug_resp_bits_resp};
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assign debug_resp_ready = dtm_resp_ready;
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`endif // !`ifdef VERILOG_DEBUG_SYNC
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//-----------------------------------------------
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// Start the simulation
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// Read input arguments and initialize
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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`ifdef DEBUG
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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if ($value$plusargs("vcdfile=%s", vcdfile))
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begin
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$dumpfile(vcdfile);
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$dumpvars(0, dut);
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$dumpon;
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end
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
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`define VCDPLUSCLOSE
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`endif
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// Strobe reset
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#777.7 reset = 0;
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end
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reg [255:0] reason = 0;
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always @(posedge clk)
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begin
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if (max_cycles > 0 && trace_count > max_cycles)
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reason = "timeout";
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if (exit > 1)
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$sformat(reason, "tohost = %d", exit >> 1);
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if (reason)
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begin
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$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
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`VCDPLUSCLOSE
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$fatal;
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end
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if (exit == 1)
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begin
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if (verbose)
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$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
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`VCDPLUSCLOSE
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$finish;
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end
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end
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count-1);
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end
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`endif
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end
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endmodule
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