2017-02-09 22:59:09 +01:00
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// See LICENSE.SiFive for license details.
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.tile
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2017-02-09 22:59:09 +01:00
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import Chisel._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.config._
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2017-12-28 23:00:13 +01:00
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import freechips.rocketchip.coreplex._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.diplomacy._
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2017-12-14 04:00:29 +01:00
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import freechips.rocketchip.interrupts._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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2017-02-09 22:59:09 +01:00
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case object SharedMemoryTLEdge extends Field[TLEdgeOut]
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case object TileKey extends Field[TileParams]
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2017-04-28 00:22:52 +02:00
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case object ResetVectorBits extends Field[Int]
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case object MaxHartIdBits extends Field[Int]
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2017-02-09 22:59:09 +01:00
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trait TileParams {
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val core: CoreParams
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val icache: Option[ICacheParams]
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val dcache: Option[DCacheParams]
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val rocc: Seq[RoCCParams]
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val btb: Option[BTBParams]
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2017-09-20 07:59:28 +02:00
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val trace: Boolean
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2017-12-21 02:18:38 +01:00
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val hartId: Int
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2017-11-18 02:26:48 +01:00
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val blockerCtrlAddr: Option[BigInt]
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2017-02-09 22:59:09 +01:00
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}
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trait HasTileParameters {
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implicit val p: Parameters
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2017-09-02 02:50:54 +02:00
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def tileParams: TileParams = p(TileKey)
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def usingVM: Boolean = tileParams.core.useVM
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def usingUser: Boolean = tileParams.core.useUser || usingVM
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def usingDebug: Boolean = tileParams.core.useDebug
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def usingRoCC: Boolean = !tileParams.rocc.isEmpty
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def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
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def usingPTW: Boolean = usingVM
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def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined
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def xLen: Int = p(XLen)
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def xBytes: Int = xLen / 8
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2017-09-20 07:59:28 +02:00
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def iLen: Int = 32
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2017-09-02 02:50:54 +02:00
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def pgIdxBits: Int = 12
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def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
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2017-10-08 02:33:36 +02:00
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def vaddrBits: Int =
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if (usingVM) {
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val v = pgIdxBits + pgLevels * pgLevelBits
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require(v == xLen || xLen > v && v > paddrBits)
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v
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} else {
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2017-10-10 01:48:04 +02:00
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// since virtual addresses sign-extend but physical addresses
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// zero-extend, make room for a zero sign bit for physical addresses
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(paddrBits + 1) min xLen
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2017-10-08 02:33:36 +02:00
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}
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2017-09-02 02:50:54 +02:00
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def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
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def vpnBits: Int = vaddrBits - pgIdxBits
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def ppnBits: Int = paddrBits - pgIdxBits
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def pgLevels: Int = p(PgLevels)
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def asIdBits: Int = p(ASIdBits)
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def vpnBitsExtended: Int = vpnBits + (vaddrBits < xLen).toInt
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def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
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def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
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2017-12-21 02:18:38 +01:00
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def hartId: Int = tileParams.hartId
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2017-09-02 02:50:54 +02:00
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def hartIdLen: Int = p(MaxHartIdBits)
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2017-10-08 02:33:36 +02:00
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def resetVectorLen: Int = paddrBits
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2017-02-09 22:59:09 +01:00
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2017-12-21 02:18:38 +01:00
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def cacheBlockBytes = p(CacheBlockBytes)
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def lgCacheBlockBytes = log2Up(cacheBlockBytes)
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def masterPortBeatBytes = p(SystemBusKey).beatBytes
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2017-02-09 22:59:09 +01:00
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def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
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2017-12-21 02:18:38 +01:00
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// TODO merge with isaString in CSR.scala
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def isaDTS: String = {
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val m = if (tileParams.core.mulDiv.nonEmpty) "m" else ""
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val a = if (tileParams.core.useAtomics) "a" else ""
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val f = if (tileParams.core.fpu.nonEmpty) "f" else ""
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val d = if (tileParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
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val c = if (tileParams.core.useCompressed) "c" else ""
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s"rv${p(XLen)}i$m$a$f$d$c"
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}
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def tileProperties: PropertyMap = {
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val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
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"d-cache-block-size" -> cacheBlockBytes.asProperty,
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"d-cache-sets" -> d.nSets.asProperty,
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"d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty)
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).getOrElse(Nil)
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val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map(
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"sifive,d-cache-incoherent" -> Nil)
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val icache = tileParams.icache.map(i => Map(
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"i-cache-block-size" -> cacheBlockBytes.asProperty,
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"i-cache-sets" -> i.nSets.asProperty,
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"i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty)
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).getOrElse(Nil)
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val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map(
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"d-tlb-size" -> d.nTLBEntries.asProperty,
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"d-tlb-sets" -> 1.asProperty)).getOrElse(Nil)
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val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map(
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"i-tlb-size" -> i.nTLBEntries.asProperty,
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"i-tlb-sets" -> 1.asProperty)).getOrElse(Nil)
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val mmu = if (!tileParams.core.useVM) Nil else Map(
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"tlb-split" -> Nil,
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"mmu-type" -> (p(PgLevels) match {
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case 2 => "riscv,sv32"
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case 3 => "riscv,sv39"
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case 4 => "riscv,sv48"
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}).asProperty)
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dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ incoherent
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}
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2017-02-09 22:59:09 +01:00
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}
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2017-04-28 00:22:52 +02:00
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/** Base class for all Tiles that use TileLink */
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2018-01-03 00:37:31 +01:00
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abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
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(implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
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{
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2018-01-03 02:55:54 +01:00
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def module: BaseTileModuleImp[BaseTile]
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2017-12-21 02:18:38 +01:00
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def masterNode: TLOutwardNode
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def slaveNode: TLInwardNode
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def intInwardNode: IntInwardNode
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def intOutwardNode: IntOutwardNode
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protected val tlOtherMastersNode = TLIdentityNode()
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protected val tlMasterXbar = LazyModule(new TLXbar)
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protected val tlSlaveXbar = LazyModule(new TLXbar)
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protected val intXbar = LazyModule(new IntXbar)
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def connectTLSlave(node: TLNode, bytes: Int) {
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DisableMonitors { implicit p =>
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(Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
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++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
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.foldRight(tlSlaveXbar.node:TLOutwardNode)(_ :*= _)
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}
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}
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// Find resource labels for all the outward caches
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def nextLevelCacheProperty: PropertyOption = {
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val outer = tlMasterXbar.node.edges.out
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.flatMap(_.manager.managers)
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.filter(_.supportsAcquireB)
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.flatMap(_.resources.headOption)
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.map(_.owner.label)
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.distinct
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if (outer.isEmpty) None
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else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
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}
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def toDescription(resources: ResourceBindings)(compat: String, extraProperties: PropertyMap = Nil): Description = {
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val cpuProperties: PropertyMap = Map(
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"reg" -> resources("reg").map(_.value),
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"device_type" -> "cpu".asProperty,
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"compatible" -> Seq(ResourceString(compat), ResourceString("riscv")),
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"status" -> "okay".asProperty,
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"clock-frequency" -> tileParams.core.bootFreqHz.asProperty,
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"riscv,isa" -> isaDTS.asProperty,
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"timebase-frequency" -> p(DTSTimebase).asProperty)
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Description(s"cpus/cpu@${hartId}", (cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ extraProperties).toMap)
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}
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2017-02-09 22:59:09 +01:00
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}
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2018-01-03 02:55:54 +01:00
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class BaseTileModuleImp[+L <: BaseTile](val outer: L) extends LazyModuleImp(outer) with HasTileParameters {
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2017-02-09 22:59:09 +01:00
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2017-09-02 02:50:54 +02:00
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require(xLen == 32 || xLen == 64)
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require(paddrBits <= maxPAddrBits)
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require(resetVectorLen <= xLen)
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require(resetVectorLen <= vaddrBitsExtended)
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2017-12-21 02:18:38 +01:00
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require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
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2018-01-03 00:37:31 +01:00
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val trace = tileParams.trace.option(IO(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput))
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val constants = IO(new TileInputConstants)
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2018-01-03 01:03:05 +01:00
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val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
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2017-09-02 02:50:54 +02:00
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}
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2018-01-03 00:37:31 +01:00
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/** Some other non-tilelink but still standard inputs */
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trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
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val hartid = UInt(INPUT, hartIdLen)
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val reset_vector = UInt(INPUT, resetVectorLen)
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}
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class TileInputConstants(implicit val p: Parameters) extends ParameterizedBundle with HasExternallyDrivenTileConstants
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