124 lines
4.1 KiB
Scala
124 lines
4.1 KiB
Scala
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package groundtest
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import Chisel._
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import uncore._
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import rocket._
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import junctions.PAddrBits
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import cde.{Parameters, Field}
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case class DmaTestCase(source: Int, dest: Int, length: Int)
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object DmaTestCases {
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def apply(cases: (Int, Int, Int) *): Seq[DmaTestCase] = {
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cases.toSeq.map {
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case (source, dest, length) => DmaTestCase(source, dest, length)
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}
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}
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}
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case object DmaTestSet extends Field[Seq[DmaTestCase]]
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case object DmaTestDataStart extends Field[Int]
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case object DmaTestDataStride extends Field[Int]
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class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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with HasDmaParameters with HasCoreParameters {
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private val testSet = p(DmaTestSet)
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private val dataStart = p(DmaTestDataStart)
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private val dataStride = p(DmaTestDataStride)
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private val wordBits = 32
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private val wordBytes = wordBits / 8
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private val pAddrBits = p(PAddrBits)
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disablePorts(cache = false, dma = false, ptw = false)
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val sourceAddrs = Vec(testSet.map(test => UInt(test.source)))
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val destAddrs = Vec(testSet.map(test => UInt(test.dest)))
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val transferLengths = Vec(testSet.map(test => UInt(test.length)))
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val testIdx = Reg(init = UInt(0, log2Up(testSet.size)))
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val (s_start :: s_fill_req :: s_fill_resp :: s_copy_req :: s_copy_wait ::
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s_check_req :: s_check_resp :: s_finished :: Nil) = Enum(Bits(), 8)
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val state = Reg(init = s_start)
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val req_data = Reg(UInt(width = wordBits))
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val req_addr = Reg(UInt(width = pAddrBits))
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val bytes_left = Reg(UInt(width = pAddrBits))
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val prefetch = sourceAddrs(testIdx) === destAddrs(testIdx)
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val frontend = Module(new DmaFrontend)
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frontend.io.cpu.req.valid := (state === s_copy_req)
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frontend.io.cpu.req.bits := ClientDmaRequest(
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cmd = Mux(prefetch, DmaRequest.DMA_CMD_PFR, DmaRequest.DMA_CMD_COPY),
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src_start = sourceAddrs(testIdx),
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dst_start = destAddrs(testIdx),
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segment_size = transferLengths(testIdx))
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io.dma <> frontend.io.dma
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io.ptw <> frontend.io.ptw
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io.cache.req.valid := (state === s_fill_req) || (state === s_check_req)
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io.cache.req.bits.addr := req_addr
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io.cache.req.bits.data := req_data
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD)
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io.cache.req.bits.kill := Bool(false)
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io.cache.req.bits.phys := Bool(false)
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when (state === s_start) {
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req_addr := sourceAddrs(testIdx)
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req_data := UInt(dataStart)
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bytes_left := transferLengths(testIdx)
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state := s_fill_req
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}
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when (io.cache.req.fire()) {
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req_addr := req_addr + UInt(wordBytes)
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bytes_left := bytes_left - UInt(wordBytes)
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state := Mux(state === s_fill_req, s_fill_resp, s_check_resp)
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}
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when (state === s_fill_resp && io.cache.resp.valid) {
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req_data := req_data + UInt(dataStride)
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state := Mux(bytes_left === UInt(0), s_copy_req, s_fill_req)
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}
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when (frontend.io.cpu.req.fire()) { state := s_copy_wait }
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when (state === s_copy_wait && !frontend.io.busy) {
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req_addr := destAddrs(testIdx)
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req_data := UInt(dataStart)
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bytes_left := transferLengths(testIdx)
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state := s_check_req
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}
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when (state === s_check_resp && io.cache.resp.valid) {
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req_data := req_data + UInt(dataStride)
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when (bytes_left > UInt(0)) {
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state := s_check_req
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} .elsewhen (testIdx === UInt(testSet.size - 1)) {
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state := s_finished
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} .otherwise {
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testIdx := testIdx + UInt(1)
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state := s_start
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}
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}
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io.finished := (state === s_finished)
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testSet.foreach { case DmaTestCase(source, dest, length) =>
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require(source % wordBytes == 0, "source address must be word-aligned")
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require(dest % wordBytes == 0, "destination address must be word-aligned")
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require(length % wordBytes == 0, "transfer length must be word-aligned")
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}
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assert(!io.cache.resp.valid || !io.cache.resp.bits.has_data ||
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io.cache.resp.bits.data === req_data, "Received data does not match")
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val dma_timeout = Timer(1000, io.dma.req.fire(), io.dma.resp.fire())
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assert(!dma_timeout, "DMA request timed out")
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val cache_timeout = Timer(1000, io.cache.req.fire(), io.cache.resp.valid)
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assert(!cache_timeout, "Memory request timed out")
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}
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