2015-10-27 05:37:35 +01:00
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package groundtest
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import Chisel._
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import rocket._
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import uncore._
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import scala.util.Random
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import cde.Parameters
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2015-10-27 07:09:36 +01:00
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class GeneratorTile(id: Int, resetSignal: Bool)
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2015-10-27 05:37:35 +01:00
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(implicit val p: Parameters) extends Tile(resetSignal)(p)
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with HasGeneratorParams {
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val gen_finished = Wire(Vec(nGensPerTile, Bool()))
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2015-10-27 07:09:36 +01:00
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val arb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
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2015-10-27 05:37:35 +01:00
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for (i <- 0 until nGensPerTile) {
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val genid = id * nGensPerTile + i
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2015-10-27 07:09:36 +01:00
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val generator = Module(new UncachedTileLinkGenerator(genid))
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2015-10-27 05:37:35 +01:00
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arb.io.in(i) <> generator.io.tl
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gen_finished(i) := generator.io.finished
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}
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2015-10-27 07:09:36 +01:00
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io.uncached(0) <> arb.io.out
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io.cached(0).acquire.valid := Bool(false)
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io.cached(0).grant.ready := Bool(false)
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io.cached(0).probe.ready := Bool(false)
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io.cached(0).release.valid := Bool(false)
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assert(!io.cached(0).probe.valid, "Shouldn't be receiving probes")
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2015-10-27 05:37:35 +01:00
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val all_done = gen_finished.reduce(_ && _)
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val csr_resp_valid = Reg(Bool()) // Don't reset
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val csr_resp_data = Reg(io.host.csr.resp.bits)
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io.host.csr.req.ready := Bool(true)
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io.host.csr.resp.valid := csr_resp_valid
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io.host.csr.resp.bits := csr_resp_data
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when (io.host.csr.req.fire()) {
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val req = io.host.csr.req.bits
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csr_resp_valid := Bool(true)
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csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), all_done, req.data)
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}
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when (io.host.csr.resp.fire()) {
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csr_resp_valid := Bool(false)
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}
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}
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