1
0
rocket-chip/README.md

77 lines
1.4 KiB
Markdown
Raw Normal View History

2014-09-12 19:15:04 +02:00
Rocket Chip Generator
=====================
This repository contains the Rocket chip generator necessary to instantiate
the RISC-V Rocket Core.
2014-09-12 19:22:00 +02:00
2014-09-12 19:15:04 +02:00
Contributors
------------
2014-09-12 19:18:14 +02:00
- Scott Beamer
- Henry Cook
- Yunsup Lee
- Stephen Twigg
- Huy Vo
- Andrew Waterman
2014-09-12 19:15:04 +02:00
2014-08-07 23:50:31 +02:00
Checkout The Code
-----------------
$ git submodule update --init --recursive
Building The Toolchain
----------------------
To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:
$ export RISCV=/path/to/riscv/toolchain/installation
$ cd riscv-tools
$ ./build.sh
Building The Project
--------------------
To build the C simulator:
$ cd emulator
$ make
To build the VCS simulator:
2014-09-01 05:57:16 +02:00
$ cd vsim
2014-08-07 23:50:31 +02:00
$ make
in either case, you can run a set of assembly tests or simple benchmarks:
$ make run-asm-tests
$ make run-bmarks-test
To build a C simulator that is capable of VCD waveform generation:
$ cd emulator
2014-09-12 09:19:29 +02:00
$ make debug
2014-08-07 23:50:31 +02:00
And to run the assembly tests on the C simulator and generate waveforms:
$ make run-asm-tests-debug
$ make run-bmarks-test-debug
2014-09-01 05:57:16 +02:00
To get FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
2014-08-07 23:52:56 +02:00
2014-09-01 05:57:16 +02:00
$ cd fsim
2014-09-12 09:19:29 +02:00
$ make verilog
2014-08-07 23:52:56 +02:00
2014-08-07 23:50:31 +02:00
Updating To A Newer Version Of Chisel
-------------------------------------
To grab a newer version of chisel:
$ git submodule update --init
$ cd chisel
$ git pull origin master