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rocket-chip/fsim/Makefrag

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update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
# Verilog sources
sim_vsrcs = \
add CONFIG to the name of simulator executable
2014-09-12 07:11:58 +02:00
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/consts.$(CONFIG).vh \
$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
add Zscale testing
2015-07-17 21:02:02 +02:00
$(base_dir)/vsrc/$(TB).v \
generate consts.vh from chisel source
2014-09-11 02:14:55 +02:00
$(base_dir)/vsrc/backup_mem.v \
update for rocket-chip release
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# C sources
sim_csrcs = \
$(base_dir)/csrc/vcs_main.cc \
$(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \
fix problem introduced with verilog generation in vsim/fsim
2014-09-04 18:49:57 +02:00
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
update for rocket-chip release
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#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
VCS = vcs -full64
error out for PCWM-L, port width mismatch
2014-09-25 15:43:03 +02:00
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
update for rocket-chip release
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+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-I$(realpath $(base_dir))/dramsim2" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
-e vcs_main \
$(RISCV)/lib/libfesvr.so \
$(sim_dir)/libdramsim.a \
+define+FPGA \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
add Zscale testing
2015-07-17 21:02:02 +02:00
+define+PRINTF_COND=$(TB).verbose \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
+libext+.v \
#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------
Get rid of MemIO in Top and replace with AXI throughout
2015-10-14 20:33:18 +02:00
simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
cd $(sim_dir) && \
$(VCS) $(VCS_OPTS) -o $(simv) \
Massive update containing several months of changes from the now-defunct private chip repo. * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
2015-06-26 08:17:35 +02:00
-debug_pp \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Get rid of MemIO in Top and replace with AXI throughout
2015-10-14 20:33:18 +02:00
simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
cd $(sim_dir) && \
$(VCS) $(VCS_OPTS) -o $(simv_debug) \
+define+DEBUG -debug_pp \
# +define+MEM_BACKUP_EN \
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
seed = $(shell date +%s)
exec_simv = $(simv) -q +ntb_random_seed_automatic
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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