47 lines
1.9 KiB
Scala
47 lines
1.9 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
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def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(po, pi)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
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TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
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bi <> bo
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val mask = ~UInt(ei.manager.beatBytes - 1)
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bi.a.bits.address := (mask & bo.a.bits.address)
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bo.b.bits.address := (mask & bi.b.bits.address)
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bi.c.bits.address := (mask & bo.c.bits.address)
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}
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}
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
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case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes), numPorts)
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case class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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