2016-07-14 21:18:11 +02:00
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package groundtest.unittests
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import Chisel._
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import junctions._
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2016-07-15 23:20:50 +02:00
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import junctions.NastiConstants._
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2016-07-15 20:08:02 +02:00
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import groundtest.common._
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2016-07-14 21:18:11 +02:00
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import cde.Parameters
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2016-07-15 20:08:02 +02:00
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class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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val dataBytes = dataWidth / 8
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val nastiDataBytes = nastiXDataBits / 8
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val (write_cnt, write_done) = Counter(io.nasti.w.fire(), burstLen)
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val (read_cnt, read_done) = Counter(io.nasti.r.fire(), burstLen)
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val (req_cnt, reqs_done) = Counter(read_done, nBursts)
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val req_addr = Cat(req_cnt, UInt(0, log2Up(burstLen * dataBytes)))
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val write_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, write_cnt)
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val expected_data = UInt(0x10000000L, dataWidth) | Cat(req_cnt, read_cnt)
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val (s_idle :: s_write_addr :: s_write_data :: s_write_stall :: s_write_resp ::
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s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9)
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val state = Reg(init = s_idle)
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val (stall_cnt, stall_done) = Counter(state === s_read_stall, 2)
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Cat(write_data, write_data),
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last = (write_cnt === UInt(burstLen - 1)))
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = req_addr,
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size = UInt(log2Up(dataBytes)),
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len = UInt(burstLen - 1))
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io.nasti.r.ready := (state === s_read_data)
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io.finished := (state === s_done)
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_stall }
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when (state === s_write_stall) { state := s_write_data }
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when (write_done) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_data }
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when (io.nasti.r.fire()) { state := s_read_stall }
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when (stall_done) { state := s_read_data }
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when (read_done) { state := s_write_addr }
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when (reqs_done) { state := s_done }
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val full_addr = req_addr + (read_cnt << UInt(log2Up(dataBytes)))
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val byteshift = full_addr(log2Up(nastiDataBytes) - 1, 0)
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val bitshift = Cat(byteshift, UInt(0, 3))
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val read_data = (io.nasti.r.bits.data >> bitshift) & Fill(dataWidth, UInt(1, 1))
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assert(!io.nasti.r.valid || read_data === expected_data,
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s"NastiDriver got wrong data")
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val ar_timeout = Timer(1024, io.nasti.ar.fire(), io.nasti.r.fire())
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val aw_timeout = Timer(1024, io.nasti.aw.fire(), io.nasti.b.fire())
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assert(!ar_timeout && !aw_timeout,
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s"NastiDriver for $name timed out")
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}
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2016-07-14 21:18:11 +02:00
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2016-07-16 00:41:15 +02:00
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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2016-07-14 21:18:11 +02:00
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}
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2016-07-15 23:20:50 +02:00
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class AtosConverterTest(implicit val p: Parameters) extends UnitTest
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with HasNastiParameters {
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val frontend = Module(new NastiDriver(nastiXDataBits, 4, 1))
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val backend = Module(new AtosConverterTestBackend)
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2016-07-15 20:08:02 +02:00
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2016-07-15 23:20:50 +02:00
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val serdes = Module(new AtosSerdes(8))
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val desser = Module(new AtosDesser(8))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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serdes.io.wide <> client_conv.io.atos
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desser.io.narrow <> serdes.io.narrow
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manager_conv.io.atos <> desser.io.wide
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backend.io.nasti <> manager_conv.io.nasti
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2016-07-16 00:41:15 +02:00
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frontend.io.start := io.start
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2016-07-15 23:20:50 +02:00
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io.finished := frontend.io.finished && backend.io.finished
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2016-07-15 20:08:02 +02:00
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}
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2016-07-15 23:20:50 +02:00
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2016-07-16 00:41:15 +02:00
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class HastiTest(implicit p: Parameters) extends UnitTest {
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val sram = Module(new HastiTestSRAM(8))
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val bus = Module(new HastiBus(Seq(a => Bool(true))))
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val conv = Module(new HastiMasterIONastiIOConverter)
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val driver = Module(new NastiDriver(32, 8, 2))
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bus.io.slaves(0) <> sram.io
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bus.io.master <> conv.io.hasti
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conv.io.nasti <> driver.io.nasti
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io.finished := driver.io.finished
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driver.io.start := io.start
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}
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2016-07-15 23:20:50 +02:00
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