25 lines
666 B
Scala
25 lines
666 B
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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regionType = RegionType.UNCACHED,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))) // requests are handled in order
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lazy val module = Module(new TLModule(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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// do stuff
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})
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}
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