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rocket-chip/rocket/src/main/scala/instructions.scala

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change package name and sbt project name to rocket
2012-02-26 02:09:26 +01:00
package rocket
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
import Chisel._
constants as traits
2012-10-08 05:15:54 +02:00
import Node._
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
object Instructions
{
Reflect ISA changes
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/* Automatically generated by parse-opcodes */
def J = Bits("b?????????????????????????1101011")
def JAL = Bits("b?????????????????????????1101111")
def JALR = Bits("b??????????????????????0001100111")
def BEQ = Bits("b??????????????????????0001100011")
def BNE = Bits("b??????????????????????0011100011")
def BLT = Bits("b??????????????????????1001100011")
def BGE = Bits("b??????????????????????1011100011")
def BLTU = Bits("b??????????????????????1101100011")
def BGEU = Bits("b??????????????????????1111100011")
def LUI = Bits("b?????????????????????????0110111")
def AUIPC = Bits("b?????????????????????????0010111")
def ADDI = Bits("b??????????????????????0000010011")
def SLLI = Bits("b??????????000000??????0010010011")
def SLTI = Bits("b??????????????????????0100010011")
def SLTIU = Bits("b??????????????????????0110010011")
def XORI = Bits("b??????????????????????1000010011")
def SRLI = Bits("b??????????000000??????1010010011")
def SRAI = Bits("b??????????000001??????1010010011")
def ORI = Bits("b??????????????????????1100010011")
def ANDI = Bits("b??????????????????????1110010011")
def ADD = Bits("b???????????????00000000000110011")
def SUB = Bits("b???????????????10000000000110011")
def SLL = Bits("b???????????????00000000010110011")
def SLT = Bits("b???????????????00000000100110011")
def SLTU = Bits("b???????????????00000000110110011")
def XOR = Bits("b???????????????00000001000110011")
def SRL = Bits("b???????????????00000001010110011")
def SRA = Bits("b???????????????10000001010110011")
def OR = Bits("b???????????????00000001100110011")
def AND = Bits("b???????????????00000001110110011")
def MUL = Bits("b???????????????00000010000110011")
def MULH = Bits("b???????????????00000010010110011")
def MULHSU = Bits("b???????????????00000010100110011")
def MULHU = Bits("b???????????????00000010110110011")
def DIV = Bits("b???????????????00000011000110011")
def DIVU = Bits("b???????????????00000011010110011")
def REM = Bits("b???????????????00000011100110011")
def REMU = Bits("b???????????????00000011110110011")
def ADDIW = Bits("b??????????????????????0000011011")
def SLLIW = Bits("b??????????0000000?????0010011011")
def SRLIW = Bits("b??????????0000000?????1010011011")
def SRAIW = Bits("b??????????0000010?????1010011011")
def ADDW = Bits("b???????????????00000000000111011")
def SUBW = Bits("b???????????????10000000000111011")
def SLLW = Bits("b???????????????00000000010111011")
def SRLW = Bits("b???????????????00000001010111011")
def SRAW = Bits("b???????????????10000001010111011")
def MULW = Bits("b???????????????00000010000111011")
def DIVW = Bits("b???????????????00000011000111011")
def DIVUW = Bits("b???????????????00000011010111011")
def REMW = Bits("b???????????????00000011100111011")
def REMUW = Bits("b???????????????00000011110111011")
def LB = Bits("b??????????????????????0000000011")
def LH = Bits("b??????????????????????0010000011")
def LW = Bits("b??????????????????????0100000011")
def LD = Bits("b??????????????????????0110000011")
def LBU = Bits("b??????????????????????1000000011")
def LHU = Bits("b??????????????????????1010000011")
def LWU = Bits("b??????????????????????1100000011")
def SB = Bits("b??????????????????????0000100011")
def SH = Bits("b??????????????????????0010100011")
def SW = Bits("b??????????????????????0100100011")
def SD = Bits("b??????????????????????0110100011")
def AMOADD_W = Bits("b???????????????00000000100101011")
def AMOSWAP_W = Bits("b???????????????00000010100101011")
def AMOAND_W = Bits("b???????????????00000100100101011")
def AMOOR_W = Bits("b???????????????00000110100101011")
def AMOMIN_W = Bits("b???????????????00001000100101011")
def AMOMAX_W = Bits("b???????????????00001010100101011")
def AMOMINU_W = Bits("b???????????????00001100100101011")
def AMOMAXU_W = Bits("b???????????????00001110100101011")
def AMOADD_D = Bits("b???????????????00000000110101011")
def AMOSWAP_D = Bits("b???????????????00000010110101011")
def AMOAND_D = Bits("b???????????????00000100110101011")
def AMOOR_D = Bits("b???????????????00000110110101011")
def AMOMIN_D = Bits("b???????????????00001000110101011")
def AMOMAX_D = Bits("b???????????????00001010110101011")
def AMOMINU_D = Bits("b???????????????00001100110101011")
def AMOMAXU_D = Bits("b???????????????00001110110101011")
def LR_W = Bits("b??????????0000010000000100101011")
def LR_D = Bits("b??????????0000010000000110101011")
def SC_W = Bits("b???????????????10000010100101011")
def SC_D = Bits("b???????????????10000010110101011")
def FENCE_I = Bits("b??????????????????????0010101111")
def FENCE = Bits("b??????????????????????0100101111")
def FENCE_V_L = Bits("b??????????????????????1000101111")
def FENCE_V_G = Bits("b??????????????????????1010101111")
def SYSCALL = Bits("b00000000000000000000000001110111")
def BREAK = Bits("b00000000000000000000000011110111")
def RDCYCLE = Bits("b?????000000000000000001001110111")
def RDTIME = Bits("b?????000000000000000011001110111")
def RDINSTRET = Bits("b?????000000000000000101001110111")
def MTPCR = Bits("b???????????????00000000001110011")
def MFPCR = Bits("b??????????0000000000000011110011")
def SETPCR = Bits("b??????????????????????0101110011")
def CLEARPCR = Bits("b??????????????????????0111110011")
def ERET = Bits("b00000000000000000000001001110011")
def FADD_S = Bits("b???????????????00000???001010011")
def FSUB_S = Bits("b???????????????00001???001010011")
def FMUL_S = Bits("b???????????????00010???001010011")
def FDIV_S = Bits("b???????????????00011???001010011")
def FSQRT_S = Bits("b??????????0000000100???001010011")
def FSGNJ_S = Bits("b???????????????00101000001010011")
def FSGNJN_S = Bits("b???????????????00110000001010011")
def FSGNJX_S = Bits("b???????????????00111000001010011")
def FADD_D = Bits("b???????????????00000???011010011")
def FSUB_D = Bits("b???????????????00001???011010011")
def FMUL_D = Bits("b???????????????00010???011010011")
def FDIV_D = Bits("b???????????????00011???011010011")
def FSQRT_D = Bits("b??????????0000000100???011010011")
def FSGNJ_D = Bits("b???????????????00101000011010011")
def FSGNJN_D = Bits("b???????????????00110000011010011")
def FSGNJX_D = Bits("b???????????????00111000011010011")
def FCVT_L_S = Bits("b??????????0000001000???001010011")
def FCVT_LU_S = Bits("b??????????0000001001???001010011")
def FCVT_W_S = Bits("b??????????0000001010???001010011")
def FCVT_WU_S = Bits("b??????????0000001011???001010011")
def FCVT_L_D = Bits("b??????????0000001000???011010011")
def FCVT_LU_D = Bits("b??????????0000001001???011010011")
def FCVT_W_D = Bits("b??????????0000001010???011010011")
def FCVT_WU_D = Bits("b??????????0000001011???011010011")
def FCVT_S_L = Bits("b??????????0000001100???001010011")
def FCVT_S_LU = Bits("b??????????0000001101???001010011")
def FCVT_S_W = Bits("b??????????0000001110???001010011")
def FCVT_S_WU = Bits("b??????????0000001111???001010011")
def FCVT_D_L = Bits("b??????????0000001100???011010011")
def FCVT_D_LU = Bits("b??????????0000001101???011010011")
def FCVT_D_W = Bits("b??????????0000001110???011010011")
def FCVT_D_WU = Bits("b??????????0000001111???011010011")
def FCVT_S_D = Bits("b??????????0000010001???001010011")
def FCVT_D_S = Bits("b??????????0000010000???011010011")
def FEQ_S = Bits("b???????????????10101000001010011")
def FLT_S = Bits("b???????????????10110000001010011")
def FLE_S = Bits("b???????????????10111000001010011")
def FEQ_D = Bits("b???????????????10101000011010011")
def FLT_D = Bits("b???????????????10110000011010011")
def FLE_D = Bits("b???????????????10111000011010011")
def FMIN_S = Bits("b???????????????11000000001010011")
def FMAX_S = Bits("b???????????????11001000001010011")
def FMIN_D = Bits("b???????????????11000000011010011")
def FMAX_D = Bits("b???????????????11001000011010011")
def FMV_X_S = Bits("b??????????0000011100000001010011")
def FMV_X_D = Bits("b??????????0000011100000011010011")
def FRSR = Bits("b?????000000000011101000001010011")
def FMV_S_X = Bits("b??????????0000011110000001010011")
def FMV_D_X = Bits("b??????????0000011110000011010011")
def FSSR = Bits("b??????????0000011111000001010011")
def FLW = Bits("b??????????????????????0100000111")
def FLD = Bits("b??????????????????????0110000111")
def FSW = Bits("b??????????????????????0100100111")
def FSD = Bits("b??????????????????????0110100111")
def FMADD_S = Bits("b???????????????????????001000011")
def FMSUB_S = Bits("b???????????????????????001000111")
def FNMSUB_S = Bits("b???????????????????????001001011")
def FNMADD_S = Bits("b???????????????????????001001111")
def FMADD_D = Bits("b???????????????????????011000011")
def FMSUB_D = Bits("b???????????????????????011000111")
def FNMSUB_D = Bits("b???????????????????????011001011")
def FNMADD_D = Bits("b???????????????????????011001111")
/* Automatically generated by parse-opcodes */
def STOP = Bits("b00000000000000000000001011110111")
def UTIDX = Bits("b?????000000000000000001101110111")
def MOVZ = Bits("b???????????????00000001111110111")
def MOVN = Bits("b???????????????00000011111110111")
def FMOVZ = Bits("b???????????????00000101111110111")
def FMOVN = Bits("b???????????????00000111111110111")
def VSETCFGVL = Bits("b??????????????????????1110001011")
def VSETVL = Bits("b??????????0000000000001100001011")
def VMVV = Bits("b??????????0000000000011100001011")
def VGETCFG = Bits("b?????000000000000000001000001011")
def VGETVL = Bits("b?????000000000000000011000001011")
def VF = Bits("b??????????00000???????0100001011")
def VXCPTSAVE = Bits("b00000?????0000000000000110001011")
def VXCPTRESTORE = Bits("b00000?????0000000000010110001011")
def VXCPTKILL = Bits("b00000000000000000000100110001011")
def VXCPTEVAC = Bits("b00000?????0000000000110110001011")
def VXCPTHOLD = Bits("b00000000000000000001000110001011")
def VENQCMD = Bits("b00000??????????00001010110001011")
def VENQIMM1 = Bits("b00000??????????00001100110001011")
def VENQIMM2 = Bits("b00000??????????00001110110001011")
def VENQCNT = Bits("b00000??????????00010000110001011")
def VLD = Bits("b??????????0000000000110100001111")
def VLW = Bits("b??????????0000000000100100001111")
def VLWU = Bits("b??????????0000000001100100001111")
def VLH = Bits("b??????????0000000000010100001111")
def VLHU = Bits("b??????????0000000001010100001111")
def VLB = Bits("b??????????0000000000000100001111")
def VLBU = Bits("b??????????0000000001000100001111")
def VFLD = Bits("b??????????0000000010110100001111")
def VFLW = Bits("b??????????0000000010100100001111")
def VLSTD = Bits("b???????????????00000110110001111")
def VLSTW = Bits("b???????????????00000100110001111")
def VLSTWU = Bits("b???????????????00001100110001111")
def VLSTH = Bits("b???????????????00000010110001111")
def VLSTHU = Bits("b???????????????00001010110001111")
def VLSTB = Bits("b???????????????00000000110001111")
def VLSTBU = Bits("b???????????????00001000110001111")
def VFLSTD = Bits("b???????????????00010110110001111")
def VFLSTW = Bits("b???????????????00010100110001111")
def VLSEGD = Bits("b??????????00000???00110101011011")
def VLSEGW = Bits("b??????????00000???00100101011011")
def VLSEGWU = Bits("b??????????00000???01100101011011")
def VLSEGH = Bits("b??????????00000???00010101011011")
def VLSEGHU = Bits("b??????????00000???01010101011011")
def VLSEGB = Bits("b??????????00000???00000101011011")
def VLSEGBU = Bits("b??????????00000???01000101011011")
def VFLSEGD = Bits("b??????????00000???10110101011011")
def VFLSEGW = Bits("b??????????00000???10100101011011")
def VLSEGSTD = Bits("b??????????????????00110111011011")
def VLSEGSTW = Bits("b??????????????????00100111011011")
def VLSEGSTWU = Bits("b??????????????????01100111011011")
def VLSEGSTH = Bits("b??????????????????00010111011011")
def VLSEGSTHU = Bits("b??????????????????01010111011011")
def VLSEGSTB = Bits("b??????????????????00000111011011")
def VLSEGSTBU = Bits("b??????????????????01000111011011")
def VFLSEGSTD = Bits("b??????????00000???10110111011011")
def VFLSEGSTW = Bits("b??????????00000???10100111011011")
def VSD = Bits("b??????????0000010000110100001111")
def VSW = Bits("b??????????0000010000100100001111")
def VSH = Bits("b??????????0000010000010100001111")
def VSB = Bits("b??????????0000010000000100001111")
def VFSD = Bits("b??????????0000010010110100001111")
def VFSW = Bits("b??????????0000010010100100001111")
def VSSTD = Bits("b???????????????10000110110001111")
def VSSTW = Bits("b???????????????10000100110001111")
def VSSTH = Bits("b???????????????10000010110001111")
def VSSTB = Bits("b???????????????10000000110001111")
def VFSSTD = Bits("b???????????????10010110110001111")
def VFSSTW = Bits("b???????????????10010100110001111")
def VSSEGD = Bits("b??????????00000???00110101111011")
def VSSEGW = Bits("b??????????00000???00100101111011")
def VSSEGH = Bits("b??????????00000???00010101111011")
def VSSEGB = Bits("b??????????00000???00000101111011")
def VFSSEGD = Bits("b??????????00000???10110101111011")
def VFSSEGW = Bits("b??????????00000???10100101111011")
def VSSEGSTD = Bits("b??????????????????00110111111011")
def VSSEGSTW = Bits("b??????????????????00100111111011")
def VSSEGSTH = Bits("b??????????????????00010111111011")
def VSSEGSTB = Bits("b??????????????????00000111111011")
def VFSSEGSTD = Bits("b??????????00000???10110111111011")
def VFSSEGSTW = Bits("b??????????00000???10100111111011")
Add RISC-V instruction disassembler
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}
object Disassemble
{
initial attempt at upgrade
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def apply(insn: UInt) = {
Add RISC-V instruction disassembler
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val name :: fmt :: Nil = ListLookup(insn, default, table)
sprintf("%s %s", name, operands(insn, fmt))
}
private def operands(insn: Bits, fmt: Bits): Bits = {
val x = AVec(Str(" x0"), Str(" ra"), Str(" s0"), Str(" s1"),
Str(" s2"), Str(" s3"), Str(" s4"), Str(" s5"),
Str(" s6"), Str(" s7"), Str(" s8"), Str(" s9"),
Str("s10"), Str("s11"), Str(" sp"), Str(" tp"),
Str(" v0"), Str(" v1"), Str(" a0"), Str(" a1"),
Str(" a2"), Str(" a3"), Str(" a4"), Str(" a5"),
Reflect ISA changes
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Str(" a6"), Str(" a7"), Str(" t0"), Str(" t1"),
Str(" t2"), Str(" t3"), Str(" t4"), Str(" t5"))
Add RISC-V instruction disassembler
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val f = AVec(Str(" fs0"), Str(" fs1"), Str(" fs2"), Str(" fs3"),
Str(" fs4"), Str(" fs5"), Str(" fs6"), Str(" fs7"),
Str(" fs8"), Str(" fs9"), Str("fs10"), Str("fs11"),
Str("fs12"), Str("fs13"), Str("fs14"), Str("fs15"),
Str(" fv0"), Str(" fv1"), Str(" fa0"), Str(" fa1"),
Str(" fa2"), Str(" fa3"), Str(" fa4"), Str(" fa5"),
Reflect ISA changes
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Str(" fa6"), Str(" fa7"), Str(" ft0"), Str(" ft1"),
Str(" ft2"), Str(" ft3"), Str(" ft4"), Str(" ft5"))
Add RISC-V instruction disassembler
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initial attempt at upgrade
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def hex(x: SInt, plus: Char = ' ') =
Cat(Mux(x < SInt(0), Str("-0x"), Str(plus + "0x")), Str(x.abs, 16))
Add RISC-V instruction disassembler
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val comma = Str(',')
val lparen = Str('(')
val rparen = Str(')')
val rd = insn(31,27)
val rs1 = insn(26,22)
val rs2 = insn(21,17)
val rs3 = insn(16,12)
initial attempt at upgrade
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val immv = insn(21,10).toSInt
val bmmv = Cat(insn(31,27), insn(16,10)).toSInt
val jmmv = insn(31,7).toSInt
Add RISC-V instruction disassembler
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Reflect ISA changes
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val imm = hex(Mux(fmt === FMT_B, bmmv << UInt(1),
Mux(fmt === FMT_I || fmt === FMT_LD || fmt === FMT_FLD, immv,
Mux(fmt === FMT_ST || fmt === FMT_FST, bmmv,
SInt(0)))))
initial attempt at upgrade
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val jmm = hex(jmmv << UInt(1))
val lmm = Cat(Str("0x"), Str(insn(26,7).toUInt, 16))
Add RISC-V instruction disassembler
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Reflect ISA changes
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val addr = Cat(comma, imm, lparen, x(rs1), rparen)
Add RISC-V instruction disassembler
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val r0 = x(rd)
val r1 = Cat(r0, comma, x(rs1))
val r2 = Cat(r1, comma, x(rs2))
val f1 = Cat(f(rd), comma, f(rs1))
val f2 = Cat(f1, comma, f(rs2))
val f3 = Cat(f2, comma, f(rs3))
val fx = Cat(f(rd), comma, x(rs1))
val xf1 = Cat(x(rd), comma, f(rs1))
val xf2 = Cat(xf1, comma, f(rs2))
val z = Str(' ')
val i = Cat(r1, comma, imm)
Reflect ISA changes
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val b = Cat(x(rs1), comma, x(rs2), comma, imm)
Add RISC-V instruction disassembler
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val j = jmm
val l = Cat(x(rd), comma, lmm)
Reflect ISA changes
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val ld = Cat(x(rd), addr)
val st = Cat(x(rs2), addr)
val fld = Cat(f(rd), addr)
val fst = Cat(f(rs2), addr)
Add RISC-V instruction disassembler
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val amo = r2
val opts = Seq(r0, r1, r2, f1, f2, f3, fx, xf1, xf2, z, i, b, j, l, ld, st,
fld, fst, amo)
val maxLen = opts.map(_.getWidth).reduce(_ max _)
initial attempt at upgrade
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val padded = opts.map(x => x.toUInt << UInt(maxLen - x.getWidth))
AVec(padded)(fmt.toUInt)
Add RISC-V instruction disassembler
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}
Reflect ISA changes
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private def FMT_X = Bits("b?????", 5)
Add RISC-V instruction disassembler
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private def FMT_R0 = Bits(0, 5)
private def FMT_R1 = Bits(1, 5)
private def FMT_R2 = Bits(2, 5)
private def FMT_F1 = Bits(3, 5)
private def FMT_F2 = Bits(4, 5)
private def FMT_F3 = Bits(5, 5)
private def FMT_FX = Bits(6, 5)
private def FMT_XF1 = Bits(7, 5)
private def FMT_XF2 = Bits(8, 5)
private def FMT_0 = Bits(9, 5)
private def FMT_I = Bits(10, 5)
private def FMT_B = Bits(11, 5)
private def FMT_J = Bits(12, 5)
private def FMT_L = Bits(13, 5)
private def FMT_LD = Bits(14, 5)
private def FMT_ST = Bits(15, 5)
private def FMT_FLD = Bits(16, 5)
private def FMT_FST = Bits(17, 5)
private def FMT_AMO = Bits(18, 5)
Reflect ISA changes
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private def default = List(Str("unknown "), FMT_0)
Add RISC-V instruction disassembler
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import Instructions._
private def table = Array(
Reflect ISA changes
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BNE-> List(Str("bne "), FMT_B),
BEQ-> List(Str("beq "), FMT_B),
BLT-> List(Str("blt "), FMT_B),
BLTU-> List(Str("bltu "), FMT_B),
BGE-> List(Str("bge "), FMT_B),
BGEU-> List(Str("bgeu "), FMT_B),
Add RISC-V instruction disassembler
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Reflect ISA changes
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J-> List(Str("j "), FMT_J),
JAL-> List(Str("jal "), FMT_J),
JALR-> List(Str("jalr "), FMT_LD),
AUIPC-> List(Str("auipc "), FMT_L),
Add RISC-V instruction disassembler
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Reflect ISA changes
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LB-> List(Str("lb "), FMT_LD),
LH-> List(Str("lh "), FMT_LD),
LW-> List(Str("lw "), FMT_LD),
LD-> List(Str("ld "), FMT_LD),
LBU-> List(Str("lbu "), FMT_LD),
LHU-> List(Str("lhu "), FMT_LD),
LWU-> List(Str("lwu "), FMT_LD),
SB-> List(Str("sb "), FMT_ST),
SH-> List(Str("sh "), FMT_ST),
SW-> List(Str("sw "), FMT_ST),
SD-> List(Str("sd "), FMT_ST),
Add RISC-V instruction disassembler
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Reflect ISA changes
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AMOADD_W-> List(Str("amoaddw "), FMT_AMO),
AMOSWAP_W-> List(Str("amoswapw"), FMT_AMO),
AMOAND_W-> List(Str("amoandw "), FMT_AMO),
AMOOR_W-> List(Str("amoorw "), FMT_AMO),
AMOMIN_W-> List(Str("amominw "), FMT_AMO),
AMOMINU_W-> List(Str("amominuw"), FMT_AMO),
AMOMAX_W-> List(Str("amomaxw "), FMT_AMO),
AMOMAXU_W-> List(Str("amomaxuw"), FMT_AMO),
AMOADD_D-> List(Str("amoaddd "), FMT_AMO),
AMOSWAP_D-> List(Str("amoswapd"), FMT_AMO),
AMOAND_D-> List(Str("amoandd "), FMT_AMO),
AMOOR_D-> List(Str("amoord "), FMT_AMO),
AMOMIN_D-> List(Str("amomind "), FMT_AMO),
AMOMINU_D-> List(Str("amominud"), FMT_AMO),
AMOMAX_D-> List(Str("amomaxd "), FMT_AMO),
AMOMAXU_D-> List(Str("amomaxud"), FMT_AMO),
Add RISC-V instruction disassembler
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Reflect ISA changes
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LR_W-> List(Str("lr.w "), FMT_AMO),
LR_D-> List(Str("lr.d "), FMT_AMO),
SC_W-> List(Str("sc.w "), FMT_AMO),
SC_D-> List(Str("sc.d "), FMT_AMO),
Add RISC-V instruction disassembler
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Reflect ISA changes
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LUI-> List(Str("lui "), FMT_L),
ADDI-> List(Str("addi "), FMT_I),
SLTI -> List(Str("slti "), FMT_I),
SLTIU-> List(Str("sltiu "), FMT_I),
ANDI-> List(Str("andi "), FMT_I),
ORI-> List(Str("ori "), FMT_I),
XORI-> List(Str("xori "), FMT_I),
SLLI-> List(Str("slli "), FMT_I),
SRLI-> List(Str("srli "), FMT_I),
SRAI-> List(Str("srai "), FMT_I),
ADD-> List(Str("add "), FMT_R2),
SUB-> List(Str("sub "), FMT_R2),
SLT-> List(Str("slt "), FMT_R2),
SLTU-> List(Str("sltu "), FMT_R2),
AND-> List(Str("and "), FMT_R2),
OR-> List(Str("or "), FMT_R2),
XOR-> List(Str("xor "), FMT_R2),
SLL-> List(Str("sll "), FMT_R2),
SRL-> List(Str("srl "), FMT_R2),
SRA-> List(Str("sra "), FMT_R2),
Add RISC-V instruction disassembler
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Reflect ISA changes
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ADDIW-> List(Str("addiw "), FMT_I),
SLLIW-> List(Str("slliw "), FMT_I),
SRLIW-> List(Str("srliw "), FMT_I),
SRAIW-> List(Str("sraiw "), FMT_I),
ADDW-> List(Str("addw "), FMT_R2),
SUBW-> List(Str("subw "), FMT_R2),
SLLW-> List(Str("sllw "), FMT_R2),
SRLW-> List(Str("srlw "), FMT_R2),
SRAW-> List(Str("sraw "), FMT_R2),
Add RISC-V instruction disassembler
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Reflect ISA changes
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MUL-> List(Str("mul "), FMT_R2),
MULH-> List(Str("mulh "), FMT_R2),
MULHU-> List(Str("mulhu "), FMT_R2),
MULHSU-> List(Str("mulhsu "), FMT_R2),
MULW-> List(Str("mulw "), FMT_R2),
Add RISC-V instruction disassembler
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Reflect ISA changes
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DIV-> List(Str("div "), FMT_R2),
DIVU-> List(Str("divu "), FMT_R2),
REM-> List(Str("rem "), FMT_R2),
REMU-> List(Str("remu "), FMT_R2),
DIVW-> List(Str("divw "), FMT_R2),
DIVUW-> List(Str("divuw "), FMT_R2),
REMW-> List(Str("remw "), FMT_R2),
REMUW-> List(Str("remuw "), FMT_R2),
Add RISC-V instruction disassembler
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Reflect ISA changes
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SYSCALL-> List(Str("syscall "), FMT_0),
SETPCR-> List(Str("setpcr "), FMT_I),
CLEARPCR-> List(Str("clearpcr"), FMT_I),
ERET-> List(Str("eret "), FMT_0),
FENCE-> List(Str("fence "), FMT_0),
FENCE_I-> List(Str("fence.i "), FMT_0),
MFPCR-> List(Str("mfpcr "), FMT_R2),
MTPCR-> List(Str("mtpcr "), FMT_R2),
RDTIME-> List(Str("rdtime "), FMT_R0),
RDCYCLE-> List(Str("rdcycle "), FMT_R0),
RDINSTRET-> List(Str("rdinstrt"), FMT_R0),
Add RISC-V instruction disassembler
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Reflect ISA changes
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FCVT_S_D-> List(Str("fcvt.sd "), FMT_F1),
FCVT_D_S-> List(Str("fcvt.ds "), FMT_F1),
FSGNJ_S-> List(Str("fsgnj.s "), FMT_F2),
FSGNJ_D-> List(Str("fsgnj.d "), FMT_F2),
FSGNJX_S-> List(Str("fsgnx.s "), FMT_F2),
FSGNJX_D-> List(Str("fsgnx.d "), FMT_F2),
FSGNJN_S-> List(Str("fsgnjn.s"), FMT_F2),
FSGNJN_D-> List(Str("fsgnjn.d"), FMT_F2),
FMIN_S-> List(Str("fmin.s "), FMT_F2),
FMIN_D-> List(Str("fmin.d "), FMT_F2),
FMAX_S-> List(Str("fmax.s "), FMT_F2),
FMAX_D-> List(Str("fmax.d "), FMT_F2),
FADD_S-> List(Str("fadd.s "), FMT_F2),
FADD_D-> List(Str("fadd.d "), FMT_F2),
FSUB_S-> List(Str("fsub.s "), FMT_F2),
FSUB_D-> List(Str("fsub.d "), FMT_F2),
FMUL_S-> List(Str("fmul.s "), FMT_F2),
FMUL_D-> List(Str("fmul.d "), FMT_F2),
FMADD_S-> List(Str("fmadd.s "), FMT_F3),
FMADD_D-> List(Str("fmadd.d "), FMT_F3),
FMSUB_S-> List(Str("fmsub.s "), FMT_F3),
FMSUB_D-> List(Str("fmsub.d "), FMT_F3),
FNMADD_S-> List(Str("fnmadd.s"), FMT_F3),
FNMADD_D-> List(Str("fnmadd.d"), FMT_F3),
FNMSUB_S-> List(Str("fnmsub.s"), FMT_F3),
FNMSUB_D-> List(Str("fnmsub.d"), FMT_F3),
FMV_X_S-> List(Str("fmv.x.s "), FMT_XF1),
FMV_X_D-> List(Str("fmv.x.d "), FMT_XF1),
FCVT_W_S-> List(Str("fcvt.ws "), FMT_XF1),
FCVT_W_D-> List(Str("fcvt.wd "), FMT_XF1),
FCVT_WU_S-> List(Str("fcvt.wus"), FMT_XF1),
FCVT_WU_D-> List(Str("fcvt.wud"), FMT_XF1),
FCVT_L_S-> List(Str("fcvt.ls "), FMT_XF1),
FCVT_L_D-> List(Str("fcvt.ld "), FMT_XF1),
FCVT_LU_S-> List(Str("fcvt.lus"), FMT_XF1),
FCVT_LU_D-> List(Str("fcvt.lud"), FMT_XF1),
FEQ_S-> List(Str("feq.s "), FMT_XF2),
FEQ_D-> List(Str("feq.d "), FMT_XF2),
FLT_S-> List(Str("flt.s "), FMT_XF2),
FLT_D-> List(Str("flt.d "), FMT_XF2),
FLE_S-> List(Str("fle.s "), FMT_XF2),
FLE_D-> List(Str("fle.d "), FMT_XF2),
FMV_S_X-> List(Str("fmv.s.x "), FMT_FX),
FMV_D_X-> List(Str("fmv.d.x "), FMT_FX),
FCVT_S_W-> List(Str("fcvt.sw "), FMT_FX),
FCVT_D_W-> List(Str("fcvt.dw "), FMT_FX),
FCVT_S_WU-> List(Str("fcvt.swu"), FMT_FX),
FCVT_D_WU-> List(Str("fcvt.dwu"), FMT_FX),
FCVT_S_L-> List(Str("fcvt.sl "), FMT_FX),
FCVT_D_L-> List(Str("fcvt.dl "), FMT_FX),
FCVT_S_LU-> List(Str("fcvt.slu"), FMT_FX),
FCVT_D_LU-> List(Str("fcvt.dlu"), FMT_FX),
FRSR-> List(Str("frsr "), FMT_R0),
FSSR-> List(Str("fssr "), FMT_R1),
FLW-> List(Str("flw "), FMT_FLD),
FLD-> List(Str("fld "), FMT_FLD),
FSW-> List(Str("fsw "), FMT_FST),
FSD-> List(Str("fsd "), FMT_FST),
Add RISC-V instruction disassembler
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Reflect ISA changes
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VSETCFGVL-> List(Str("vecInst "), FMT_0),
VSETVL-> List(Str("vecInst "), FMT_0),
VF-> List(Str("vecInst "), FMT_0),
VMVV-> List(Str("vecInst "), FMT_0),
FENCE_V_L-> List(Str("vecInst "), FMT_0),
FENCE_V_G-> List(Str("vecInst "), FMT_0),
VLD-> List(Str("vecInst "), FMT_0),
VLW-> List(Str("vecInst "), FMT_0),
VLWU-> List(Str("vecInst "), FMT_0),
VLH-> List(Str("vecInst "), FMT_0),
VLHU-> List(Str("vecInst "), FMT_0),
VLB-> List(Str("vecInst "), FMT_0),
VLBU-> List(Str("vecInst "), FMT_0),
VSD-> List(Str("vecInst "), FMT_0),
VSW-> List(Str("vecInst "), FMT_0),
VSH-> List(Str("vecInst "), FMT_0),
VSB-> List(Str("vecInst "), FMT_0),
VFLD-> List(Str("vecInst "), FMT_0),
VFLW-> List(Str("vecInst "), FMT_0),
VFSD-> List(Str("vecInst "), FMT_0),
VFSW-> List(Str("vecInst "), FMT_0),
VLSTD-> List(Str("vecInst "), FMT_0),
VLSTW-> List(Str("vecInst "), FMT_0),
VLSTWU-> List(Str("vecInst "), FMT_0),
VLSTH-> List(Str("vecInst "), FMT_0),
VLSTHU-> List(Str("vecInst "), FMT_0),
VLSTB-> List(Str("vecInst "), FMT_0),
VLSTBU-> List(Str("vecInst "), FMT_0),
VSSTD-> List(Str("vecInst "), FMT_0),
VSSTW-> List(Str("vecInst "), FMT_0),
VSSTH-> List(Str("vecInst "), FMT_0),
VSSTB-> List(Str("vecInst "), FMT_0),
VFLSTD-> List(Str("vecInst "), FMT_0),
VFLSTW-> List(Str("vecInst "), FMT_0),
VFSSTD-> List(Str("vecInst "), FMT_0),
VFSSTW-> List(Str("vecInst "), FMT_0),
Add RISC-V instruction disassembler
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Reflect ISA changes
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VENQCMD-> List(Str("vecInst "), FMT_0),
VENQIMM1-> List(Str("vecInst "), FMT_0),
VENQIMM2-> List(Str("vecInst "), FMT_0),
VENQCNT-> List(Str("vecInst "), FMT_0),
VXCPTEVAC-> List(Str("vecInst "), FMT_0),
VXCPTKILL-> List(Str("vecInst "), FMT_0),
VXCPTHOLD-> List(Str("vecInst "), FMT_0)
Add RISC-V instruction disassembler
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)
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
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