2016-05-03 00:19:43 +02:00
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// See LICENSE for license details.
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2016-06-28 20:21:38 +02:00
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package uncore.devices
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2016-05-03 00:19:43 +02:00
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import Chisel._
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2016-09-02 23:48:16 +02:00
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import rocket.Util._
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2016-05-03 00:19:43 +02:00
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import junctions._
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import junctions.NastiConstants._
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2016-06-28 20:21:38 +02:00
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import uncore.tilelink._
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2016-09-02 23:48:16 +02:00
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import uncore.util._
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2016-05-03 00:19:43 +02:00
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import cde.{Parameters, Field}
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/** Number of tiles */
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case object NTiles extends Field[Int]
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2016-05-03 02:49:10 +02:00
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class PRCITileIO(implicit p: Parameters) extends Bundle {
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val reset = Bool(OUTPUT)
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2016-09-14 01:25:31 +02:00
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val interrupts = new Bundle {
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val mtip = Bool()
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val msip = Bool()
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2016-08-23 19:54:19 +02:00
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}
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override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
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}
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2016-06-28 08:05:48 +02:00
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object PRCI {
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def msip(hart: Int) = hart * msipBytes
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def timecmp(hart: Int) = 0x4000 + hart * timecmpBytes
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def time = 0xbff8
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def msipBytes = 4
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def timecmpBytes = 8
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def size = 0xc000
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}
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2016-06-06 08:06:21 +02:00
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/** Power, Reset, Clock, Interrupt */
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class PRCI(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val tiles = Vec(p(NTiles), new PRCITileIO)
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val rtcTick = Bool(INPUT)
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}
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val timeWidth = 64
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val timecmp = Reg(Vec(p(NTiles), UInt(width = timeWidth)))
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val time = Reg(init=UInt(0, timeWidth))
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when (io.rtcTick) { time := time + UInt(1) }
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val ipi = Reg(init=Vec.fill(p(NTiles))(UInt(0, 32)))
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val acq = Queue(io.tl.acquire, 1)
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val addr = acq.bits.full_addr()(log2Ceil(PRCI.size)-1,0)
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val read = acq.bits.isBuiltInType(Acquire.getType)
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val rdata = Wire(init=UInt(0))
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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2016-06-28 08:05:48 +02:00
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when (addr(log2Floor(PRCI.time))) {
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require(log2Floor(PRCI.timecmp(p(NTiles)-1)) < log2Floor(PRCI.time))
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rdata := store(Seq(time), acq.bits, io.tl.grant.fire())
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}.elsewhen (addr >= PRCI.timecmp(0)) {
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rdata := store(timecmp, acq.bits, io.tl.grant.fire())
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}.otherwise {
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rdata := store(ipi, acq.bits, io.tl.grant.fire()) & Fill(tlDataBits/32, UInt(1, 32))
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}
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2016-06-06 08:06:21 +02:00
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for ((tile, i) <- io.tiles zipWithIndex) {
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tile.interrupts.msip := ipi(i)(0)
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tile.interrupts.mtip := time >= timecmp(i)
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2016-09-14 01:25:31 +02:00
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tile.reset := reset
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}
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// TODO generalize these to help other TL slaves
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def load(v: Seq[UInt], acq: Acquire): UInt = {
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val w = v.head.getWidth
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val a = acq.full_addr()
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require(isPow2(w) && w >= 8)
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if (w > tlDataBits) {
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(v(a.extract(log2Ceil(w/8*v.size)-1,log2Ceil(w/8))) >> a.extract(log2Ceil(w/8)-1,log2Ceil(tlDataBytes)))(tlDataBits-1,0)
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} else {
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val row: Seq[UInt] = for (i <- 0 until v.size by tlDataBits/w)
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yield Cat(v.slice(i, i + tlDataBits/w).reverse)
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if (row.size == 1) row.head
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else row(a(log2Ceil(w/8*v.size)-1,log2Ceil(tlDataBytes)))
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}
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}
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def store(v: Seq[UInt], acq: Acquire, en: Bool): UInt = {
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val w = v.head.getWidth
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require(isPow2(w) && w >= 8)
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val a = acq.full_addr()
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val rdata = load(v, acq)
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val wdata = (acq.data & acq.full_wmask()) | (rdata & ~acq.full_wmask())
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when (en && acq.isBuiltInType(Acquire.putType)) {
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if (w <= tlDataBits) {
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val word =
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if (tlDataBits/w >= v.size) UInt(0)
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else a(log2Up(w/8*v.size)-1,log2Up(tlDataBytes))
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for (i <- 0 until v.size) when (word === i/(tlDataBits/w)) {
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val base = i % (tlDataBits/w)
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v(i) := wdata >> (w * (i % (tlDataBits/w)))
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}
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} else {
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val i = a.extract(log2Ceil(w/8*v.size)-1,log2Ceil(w/8))
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val mask = FillInterleaved(tlDataBits, UIntToOH(a.extract(log2Ceil(w/8)-1,log2Ceil(tlDataBytes))))
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v(i) := (wdata & mask) | (v(i) & ~mask)
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2016-06-28 08:05:48 +02:00
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}
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}
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rdata
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}
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2016-05-03 00:19:43 +02:00
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}
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