2016-09-08 11:08:57 +02:00
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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2016-09-11 08:39:29 +02:00
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import cde.{Parameters, Field}
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2016-09-08 11:08:57 +02:00
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import junctions._
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2016-10-04 00:17:36 +02:00
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import diplomacy._
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2016-09-08 11:08:57 +02:00
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import uncore.tilelink._
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2016-09-15 03:09:27 +02:00
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import uncore.tilelink2._
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2016-09-11 08:39:29 +02:00
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import uncore.devices._
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2016-09-28 06:27:07 +02:00
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import util._
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2016-09-11 08:39:29 +02:00
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import rocket._
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2016-09-08 11:08:57 +02:00
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import coreplex._
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2016-09-11 08:39:29 +02:00
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// the following parameters will be refactored properly with TL2
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2016-09-15 09:38:46 +02:00
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case object GlobalAddrMap extends Field[AddrMap]
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case object NCoreplexExtClients extends Field[Int]
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2016-10-09 21:34:10 +02:00
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Bool]
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2016-09-08 11:08:57 +02:00
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/** Base Top with no Periphery */
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2016-10-27 07:28:40 +02:00
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abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit q: Parameters) extends LazyModule {
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2016-09-11 08:39:29 +02:00
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// the following variables will be refactored properly with TL2
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val pBusMasters = new RangeManager
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2016-09-15 09:38:46 +02:00
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2016-10-09 21:34:10 +02:00
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TLImp.emitMonitors = q(TLEmitMonitors)
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2016-10-25 08:56:09 +02:00
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// Add a SoC and peripheral bus
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val socBus = LazyModule(new TLXbar)
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2016-09-17 02:27:49 +02:00
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val peripheryBus = LazyModule(new TLXbar)
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2016-10-29 06:20:49 +02:00
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val intBus = LazyModule(new IntXbar)
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2016-09-17 02:27:49 +02:00
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2016-10-27 07:28:40 +02:00
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// Fill in the TL1 legacy parameters
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2016-10-28 03:03:43 +02:00
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implicit val p = q.alterPartial {
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2016-10-27 07:28:40 +02:00
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case NCoreplexExtClients => pBusMasters.sum
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2016-10-28 03:29:16 +02:00
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case GlobalAddrMap => legacyAddrMap
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2016-10-27 07:28:40 +02:00
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}
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2016-09-15 09:38:46 +02:00
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2016-10-28 03:29:16 +02:00
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val coreplex : C = LazyModule(buildCoreplex(p))
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// Create the address map for legacy masters
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lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers)
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2016-09-15 03:09:27 +02:00
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2016-09-24 00:25:58 +02:00
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peripheryBus.node :=
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2016-10-27 07:28:40 +02:00
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TLWidthWidget(p(SOCBusKey).beatBytes)(
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2016-10-29 00:05:49 +02:00
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TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
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socBus.node))
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2016-10-25 08:56:09 +02:00
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2016-10-02 11:31:30 +02:00
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TopModule.contents = Some(this)
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2016-09-11 08:39:29 +02:00
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}
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2016-09-08 11:08:57 +02:00
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2016-10-27 07:28:40 +02:00
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abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends Bundle {
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implicit val p = outer.p
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2016-09-15 21:19:22 +02:00
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val success = Bool(OUTPUT)
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2016-09-08 11:08:57 +02:00
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}
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2016-10-29 01:47:20 +02:00
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abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io: B) extends LazyModuleImp(io.outer) {
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val outer = io.outer.asInstanceOf[io.outer.type]
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2016-10-27 07:28:40 +02:00
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implicit val p = outer.p
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2016-10-28 00:34:37 +02:00
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val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
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val coreplexSlave : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
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val coreplexDebug : DebugBusIO = Wire(outer.coreplex.module.io.debug)
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2016-09-11 08:39:29 +02:00
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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2016-09-17 09:16:00 +02:00
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val prot = entry.region.attr.prot
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val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
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(if ((prot & AddrMapProt.W) > 0) "W" else "") +
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(if ((prot & AddrMapProt.X) > 0) "X" else "")
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val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
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println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
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2016-09-11 08:39:29 +02:00
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}
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2016-10-28 00:34:37 +02:00
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io.success := outer.coreplex.module.io.success
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2016-09-08 11:08:57 +02:00
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}
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2016-09-27 20:55:32 +02:00
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trait DirectConnection {
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val coreplex: BaseCoreplex
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val socBus: TLXbar
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2016-10-29 06:20:49 +02:00
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val intBus: IntXbar
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2016-10-28 00:34:37 +02:00
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socBus.node := coreplex.mmio
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2016-10-29 06:20:49 +02:00
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coreplex.mmioInt := intBus.intnode
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2016-10-28 00:34:37 +02:00
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}
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trait DirectConnectionModule {
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2016-10-27 07:28:40 +02:00
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val outer: BaseTop[BaseCoreplex]
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2016-09-27 20:55:32 +02:00
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2016-10-28 00:34:37 +02:00
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val coreplexMem : Vec[ClientUncachedTileLinkIO]
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val coreplexSlave : Vec[ClientUncachedTileLinkIO]
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val coreplexDebug : DebugBusIO
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2016-10-29 06:20:49 +02:00
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coreplexMem <> outer.coreplex.module.io.mem
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2016-10-28 00:34:37 +02:00
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outer.coreplex.module.io.slave <> coreplexSlave
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outer.coreplex.module.io.debug <> coreplexDebug
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2016-09-27 20:55:32 +02:00
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}
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