52 lines
1.8 KiB
Scala
52 lines
1.8 KiB
Scala
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import rocket.Util._
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import coreplex._
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/** Base Top with no Periphery */
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abstract class BaseTop(val p: Parameters) extends LazyModule
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class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
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val success = c.hasSuccessFlag.option(Bool(OUTPUT))
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}
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class BaseTopModule[L <: BaseTop, B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
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val coreplex = p(BuildCoreplex)(p)
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val outer: L = l
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val io: B = b(coreplex)
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io.success zip coreplex.io.success map { case (x, y) => x := y }
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coreplex.io.rtcTick := Counter(p(RTCPeriod)).inc()
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val mmioNetwork = p(ExportMMIOPort).option(
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Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
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p.alterPartial({ case TLId => "L2toMMIO" }))))
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mmioNetwork.foreach { _.io.in.head <> coreplex.io.mmio.get }
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}
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/** Example Top with Periphery */
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class ExampleTop(p: Parameters) extends BaseTop(p)
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with PeripheryDebug with PeripheryInterrupt
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with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
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lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
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}
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class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
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with PeripheryDebugBundle with PeripheryInterruptBundle
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with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
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class ExampleTopModule[L <: ExampleTop, B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
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with PeripheryDebugModule with PeripheryInterruptModule
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with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
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