206 lines
6.8 KiB
Scala
206 lines
6.8 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.math.max
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/** Options for memory regions */
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object RegionType {
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sealed trait T
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case object CACHED extends T
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case object TRACKED extends T
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case object UNCACHED extends T
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case object UNCACHEABLE extends T
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val cases = Seq(CACHED, TRACKED, UNCACHED, UNCACHEABLE)
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}
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// A non-empty half-open range; [start, end)
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case class IdRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (end >= 0)
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require (start < end) // not empty
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// This is a strict partial ordering
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def <(x: IdRange) = end <= x.start
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def >(x: IdRange) = x < this
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def overlaps(x: IdRange) = start < x.end && x.start < end
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def contains(x: IdRange) = start <= x.start && x.end <= end
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// contains => overlaps (because empty is forbidden)
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def contains(x: Int) = start <= x && x < end
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def contains(x: UInt) = UInt(start) <= x && x < UInt(end) // !!! special-case =
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def shift(x: Int) = IdRange(start+x, end+x)
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}
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// An potentially empty inclusive range of 2-powers [min, max]
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case class TransferSizes(min: Int, max: Int)
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{
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def this(x: Int) = this(x, x)
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require (min <= max)
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require (min != 0 || max == 0)
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require (max == 0 || isPow2(max))
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require (min == 0 || isPow2(min))
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def none = min == 0
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def contains(x: Int) = isPow2(x) && min <= x && x <= max
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def containsLg(x: Int) = contains(1 << x)
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def containsLg(x: UInt) = if (none) Bool(false) else { UInt(log2Ceil(min)) <= x && x <= UInt(log2Ceil(max)) } // !!! special-case =
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def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
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def intersect(x: TransferSizes) =
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if (x.max < min || min < x.max) TransferSizes.none
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else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
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}
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object TransferSizes {
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def apply(x: Int) = new TransferSizes(x)
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val none = new TransferSizes(0)
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}
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// AddressSets specify the mask of bits consumed by the manager
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// The base address used by the crossbar for routing
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case class AddressSet(mask: BigInt, base: Option[BigInt] = None)
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{
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// Forbid empty sets
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require (base == None || (base.get & mask) == 0)
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def contains(x: BigInt) = ((x ^ base.get) & ~mask) == 0
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def contains(x: UInt) = ((x ^ UInt(base.get)) & UInt(~mask)) === UInt(0)
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// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
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// if base = None, it will be auto-assigned and thus not overlap anything
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def overlaps(x: AddressSet) = (base, x.base) match {
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case (Some(tbase), Some(xbase)) => (~(mask | x.mask) & (tbase ^ xbase)) == 0
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case _ => false
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}
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// contains iff bitwise: x.mask => mask && contains(x.base)
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def contains(x: AddressSet) = ((x.mask | (base.get ^ x.base.get)) & ~mask) == 0
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// 1 less than the number of bytes to which the manager should be aligned
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def alignment1 = ((mask + 1) & ~mask) - 1
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def max = base.get | mask
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}
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case class TLManagerParameters(
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address: Seq[AddressSet],
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.UNCACHEABLE,
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// Supports both Acquire+Release of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsAtomic: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHints: Boolean = false,
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// If fifoId=Some, all messages sent to the same fifoId are delivered in FIFO order
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fifoId: Option[Int] = None)
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{
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address.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.overlaps(y))
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})
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address.foreach({ case a =>
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require (supportsAcquire.none || a.alignment1 >= supportsAcquire.max-1)
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})
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val maxTransfer = List(
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supportsAcquire.max,
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supportsAtomic.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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}
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case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)
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{
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require (isPow2(beatBytes))
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// Require disjoint ranges for Ids and addresses
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managers.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.sinkId.overlaps(y.sinkId))
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x.address.foreach({ a => y.address.foreach({ b =>
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require (!a.overlaps(b))
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})})
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})
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def endSinkId = managers.map(_.sinkId.end).max
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def maxAddress = managers.map(_.address.map(_.max).max).max
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def maxGet = managers.map(_.supportsGet.max).max
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def maxTransfer = managers.map(_.maxTransfer).max
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// These return Option[TLSinkParameters] for your convenience
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def findById(x: Int) = managers.find(_.sinkId.contains(x))
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def findByAddress(x: BigInt) = managers.find(_.address.exists(_.contains(x)))
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//def buildCacheInfo(): UInt => Chilse(RegionType) // UInt = address, not sink_id
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//def buildAtomicInfo(): UInt => Bool
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}
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case class TLClientParameters(
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sourceId: IdRange = IdRange(0,1),
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsAtomics: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHints: Boolean = false)
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{
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val maxTransfer = List(
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supportsProbe.max,
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supportsAtomics.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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}
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case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
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def endSourceId = clients.map(_.sourceId.end).max
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def maxTransfer = clients.map(_.maxTransfer).max
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// def nSources: Int = sourceView.map(_.sourceIds.count).sum
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// def nCaches: Int = sourceView.map(s => if(s.supportsProbe) 1 else 0).sum
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//def makeSourceToCache() = ...
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//def makeCacheToStartSource() = ...
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}
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case class TLBundleParameters(
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addressBits: Int,
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dataBits: Int,
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sourceBits: Int,
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sinkBits: Int,
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sizeBits: Int)
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{
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// Chisel has issues with 0-width wires
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require (addressBits >= 1)
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require (dataBits >= 1)
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require (sourceBits >= 1)
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require (sinkBits >= 1)
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require (sizeBits >= 1)
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require (isPow2(dataBits))
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def union(x: TLBundleParameters) =
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TLBundleParameters(
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max(addressBits, x.addressBits),
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max(dataBits, x.dataBits),
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max(sourceBits, x.sourceBits),
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max(sinkBits, x.sinkBits),
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max(sizeBits, x.sizeBits))
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}
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case class TLEdgeParameters(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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{
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val bundle = TLBundleParameters(
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addressBits = log2Up(manager.maxAddress + 1) - log2Up(manager.beatBytes),
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dataBits = manager.beatBytes * 8,
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sourceBits = log2Up(client.endSourceId),
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sinkBits = log2Up(manager.endSinkId),
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sizeBits = log2Up(log2Up(max(client.maxTransfer, manager.maxTransfer))+1))
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}
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