rocket-chip/vsim/Makefrag

#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------

# Verilog sources

sim_vsrcs = \
	$(generated_dir)/$(MODEL).$(CONFIG).v \
	$(generated_dir)/consts.$(CONFIG).vh \
	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
	$(base_dir)/vsrc/$(TB).v \
	$(base_dir)/vsrc/backup_mem.v \

# C sources

sim_csrcs = \
	$(base_dir)/csrc/vcs_main.$(TB).cc \
	$(base_dir)/csrc/mm.cc \
	$(base_dir)/csrc/mm_dramsim2.cc \

#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------

verilog: $(sim_vsrcs)

.PHONY: verilog

#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

VCS = vcs -full64

VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
	+rad +v2k +vcs+lic+wait \
	+vc+list -CC "-I$(VCS_HOME)/include" \
	-CC "-I$(RISCV)/include" \
	-CC "-I$(realpath $(base_dir))/dramsim2" \
	-CC "-std=c++11" \
	-CC "-Wl,-rpath,$(RISCV)/lib" \
	-CC "-include $(consts_header)" \
	-CC "-include $(scr_header)" \
	-e vcs_main \
	$(RISCV)/lib/libfesvr.so \
	$(sim_dir)/libdramsim.a \
	+incdir+$(generated_dir) \
	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
	+define+PRINTF_COND=$(TB).verbose \
	+libext+.v \

#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------

simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv) \
	-debug_pp \

simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
	+define+DEBUG -debug_pp \

#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------

seed = $(shell date +%s)
exec_simv = $(simv) -q +ntb_random_seed_automatic
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`#--------------------------------------------------------------------`
			`# Sources`
			`#--------------------------------------------------------------------`

			`# Verilog sources`

			`sim_vsrcs = \`
add CONFIG to the name of simulator executable 2014-09-12 07:11:58 +02:00			`$(generated_dir)/$(MODEL).$(CONFIG).v \`
			`$(generated_dir)/consts.$(CONFIG).vh \`
			`$(generated_dir)/memdessertMemDessert.$(CONFIG).v \`
add Zscale testing 2015-07-17 21:02:02 +02:00			`$(base_dir)/vsrc/$(TB).v \`
generate consts.vh from chisel source 2014-09-11 02:14:55 +02:00			`$(base_dir)/vsrc/backup_mem.v \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00
			`# C sources`

			`sim_csrcs = \`
Fix zscale testing Use the following command in vsim: make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests 2015-12-02 02:31:10 +01:00			`$(base_dir)/csrc/vcs_main.$(TB).cc \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`$(base_dir)/csrc/mm.cc \`
			`$(base_dir)/csrc/mm_dramsim2.cc \`

fix problem introduced with verilog generation in vsim/fsim 2014-09-04 18:49:57 +02:00			`#--------------------------------------------------------------------`
			`# Build Verilog`
			`#--------------------------------------------------------------------`

			`verilog: $(sim_vsrcs)`

			`.PHONY: verilog`

update for rocket-chip release 2014-09-01 05:26:55 +02:00			`#--------------------------------------------------------------------`
			`# Build rules`
			`#--------------------------------------------------------------------`

			`VCS = vcs -full64`

error out for PCWM-L, port width mismatch 2014-09-25 15:43:03 +02:00			`VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`+rad +v2k +vcs+lic+wait \`
			`+vc+list -CC "-I$(VCS_HOME)/include" \`
			`-CC "-I$(RISCV)/include" \`
			`-CC "-I$(realpath $(base_dir))/dramsim2" \`
			`-CC "-std=c++11" \`
			`-CC "-Wl,-rpath,$(RISCV)/lib" \`
no spaces in Makefrag 2015-11-06 01:42:05 +01:00			`-CC "-include $(consts_header)" \`
Generate and use SCR address header files This uses the new SCRFile changes to generate a header file containing a list of all the SCRs in a core to remove the magic constant "63" (the HTIF clock divider control register) and replace it with a generated number (which is still 63). 2016-02-18 00:23:18 +01:00			`-CC "-include $(scr_header)" \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`-e vcs_main \`
			`$(RISCV)/lib/libfesvr.so \`
			`$(sim_dir)/libdramsim.a \`
add multichannel NASTI support in Verilog testbench 2015-10-31 05:14:33 +01:00			`+incdir+$(generated_dir) \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \`
add Zscale testing 2015-07-17 21:02:02 +02:00			`+define+PRINTF_COND=$(TB).verbose \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`+libext+.v \`

			`#--------------------------------------------------------------------`
			`# Build the simulator`
			`#--------------------------------------------------------------------`

Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 09:23:31 +02:00			`simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)`
use definitions in consts header whenever possible 2015-11-05 19:15:02 +01:00			`$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`cd $(sim_dir) && \`
no spaces in Makefrag 2015-11-06 01:42:05 +01:00			`rm -rf csrc && \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`$(VCS) $(VCS_OPTS) -o $(simv) \`
Massive update containing several months of changes from the now-defunct private chip repo. * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules. 2015-06-26 08:17:35 +02:00			`-debug_pp \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 09:23:31 +02:00			`simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug`
use definitions in consts header whenever possible 2015-11-05 19:15:02 +01:00			`$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`cd $(sim_dir) && \`
no spaces in Makefrag 2015-11-06 01:42:05 +01:00			`rm -rf csrc && \`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`$(VCS) $(VCS_OPTS) -o $(simv_debug) \`
			`+define+DEBUG -debug_pp \`

			`#--------------------------------------------------------------------`
			`# Run`
			`#--------------------------------------------------------------------`

			`seed = $(shell date +%s)`
			`exec_simv = $(simv) -q +ntb_random_seed_automatic`
			`exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic`