2015-07-28 09:23:31 +02:00
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#--------------------------------------------------------------------
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# Verilog Generation
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#--------------------------------------------------------------------
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2016-03-06 02:19:53 +01:00
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# If I don't mark these as .SECONDARY then make will delete these internal
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# files.
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.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
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2016-09-15 02:33:39 +02:00
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firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
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2016-09-15 05:29:55 +02:00
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.PHONY: firrtl
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2016-09-15 02:33:39 +02:00
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2016-08-05 20:07:42 +02:00
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$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
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2016-03-06 02:19:53 +01:00
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mkdir -p $(dir $@)
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2016-09-01 19:28:07 +02:00
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cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
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2016-03-06 02:19:53 +01:00
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2016-09-06 23:48:28 +02:00
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$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
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2016-03-06 02:19:53 +01:00
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mkdir -p $(dir $@)
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2016-09-08 00:27:26 +02:00
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$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
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2016-09-06 23:48:28 +02:00
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2016-08-24 21:52:24 +02:00
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$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
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2016-09-06 23:48:28 +02:00
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cd $(generated_dir) && \
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2016-08-24 21:52:24 +02:00
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rm -f $@ && \
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$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
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mv $@.tmp $@
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2016-03-06 02:19:53 +01:00
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$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
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2015-07-28 09:23:31 +02:00
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echo "\`ifndef CONST_VH" > $@
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echo "\`define CONST_VH" >> $@
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sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
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echo "\`endif // CONST_VH" >> $@
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2014-09-01 05:26:55 +02:00
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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2016-08-16 07:03:03 +02:00
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$(output_dir)/%.run: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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2015-07-13 23:54:26 +02:00
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2016-08-16 07:03:03 +02:00
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$(output_dir)/%.out: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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2014-09-01 05:26:55 +02:00
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2016-08-16 07:03:03 +02:00
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$(output_dir)/%.vcd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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2014-09-01 05:26:55 +02:00
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2016-08-16 07:03:03 +02:00
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$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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2014-09-01 05:26:55 +02:00
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2016-08-16 07:03:03 +02:00
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$(output_dir)/%.saif: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
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2014-09-01 05:26:55 +02:00
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2015-09-10 07:37:47 +02:00
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run: run-asm-tests run-bmark-tests
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run-debug: run-asm-tests-debug run-bmark-tests-debug
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2015-07-13 23:54:26 +02:00
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run-fast: run-asm-tests-fast run-bmark-tests-fast
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2014-09-01 05:26:55 +02:00
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2015-07-13 23:54:26 +02:00
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.PHONY: run-asm-tests run-bmark-tests
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.PHONY: run-asm-tests-debug run-bmark-tests-debug
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.PHONY: run run-debug run-fast
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2014-09-01 05:26:55 +02:00
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junk += $(output_dir)
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