2016-01-06 05:04:49 +01:00
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package junctions
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import Chisel._
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import NastiConstants._
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import cde.Parameters
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class StreamChannel(w: Int) extends Bundle {
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val data = UInt(width = w)
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val last = Bool()
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override def cloneType = new StreamChannel(w).asInstanceOf[this.type]
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}
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class StreamIO(w: Int) extends Bundle {
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val out = Decoupled(new StreamChannel(w))
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val in = Decoupled(new StreamChannel(w)).flip
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override def cloneType = new StreamIO(w).asInstanceOf[this.type]
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}
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class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val stream = new StreamIO(w)
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}
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val streamSize = UInt(log2Up(w / 8))
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.size === streamSize,
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"read channel wrong size on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.len === UInt(0) ||
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io.nasti.ar.bits.burst === BURST_FIXED,
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2016-01-06 05:04:49 +01:00
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"read channel wrong burst type on stream")
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.size === streamSize,
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"write channel wrong size on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.len === UInt(0) ||
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io.nasti.aw.bits.burst === BURST_FIXED,
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2016-01-06 05:04:49 +01:00
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"write channel wrong burst type on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR,
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"write channel cannot take partial writes")
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2016-01-06 05:04:49 +01:00
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val read_id = Reg(io.nasti.ar.bits.id)
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2016-02-15 18:48:35 +01:00
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val read_cnt = Reg(io.nasti.ar.bits.len)
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2016-01-06 05:04:49 +01:00
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val reading = Reg(init = Bool(false))
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io.nasti.ar.ready := !reading
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io.nasti.r.valid := reading && io.stream.in.valid
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io.nasti.r.bits := io.stream.in.bits
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2016-09-13 19:47:36 +02:00
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io.nasti.r.bits.resp := RESP_OKAY
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2016-01-06 05:04:49 +01:00
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io.nasti.r.bits.id := read_id
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io.stream.in.ready := reading && io.nasti.r.ready
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when (io.nasti.ar.fire()) {
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read_id := io.nasti.ar.bits.id
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2016-02-15 18:48:35 +01:00
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read_cnt := io.nasti.ar.bits.len
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2016-01-06 05:04:49 +01:00
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reading := Bool(true)
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}
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2016-02-15 18:48:35 +01:00
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when (io.nasti.r.fire()) {
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when (read_cnt === UInt(0)) {
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reading := Bool(false)
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} .otherwise {
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read_cnt := read_cnt - UInt(1)
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}
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2016-01-06 05:04:49 +01:00
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}
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val write_id = Reg(io.nasti.aw.bits.id)
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val writing = Reg(init = Bool(false))
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val write_resp = Reg(init = Bool(false))
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io.nasti.aw.ready := !writing && !write_resp
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io.nasti.w.ready := writing && io.stream.out.ready
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io.stream.out.valid := writing && io.nasti.w.valid
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io.stream.out.bits := io.nasti.w.bits
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io.nasti.b.valid := write_resp
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2016-09-13 19:47:36 +02:00
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io.nasti.b.bits.resp := RESP_OKAY
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2016-01-06 05:04:49 +01:00
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io.nasti.b.bits.id := write_id
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when (io.nasti.aw.fire()) {
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write_id := io.nasti.aw.bits.id
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writing := Bool(true)
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}
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when (io.nasti.w.fire() && io.nasti.w.bits.last) {
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writing := Bool(false)
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write_resp := Bool(true)
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}
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when (io.nasti.b.fire()) { write_resp := Bool(false) }
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}
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2016-01-22 02:39:57 +01:00
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class StreamNarrower(win: Int, wout: Int) extends Module {
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require(win > wout, "Stream narrower input width must be larger than input width")
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require(win % wout == 0, "Stream narrower input width must be multiple of output width")
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val io = new Bundle {
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val in = Decoupled(new StreamChannel(win)).flip
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val out = Decoupled(new StreamChannel(wout))
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}
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val n_pieces = win / wout
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val buffer = Reg(Bits(width = win))
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val (piece_idx, pkt_done) = Counter(io.out.fire(), n_pieces)
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val pieces = Vec.tabulate(n_pieces) { i => buffer(wout * (i + 1) - 1, wout * i) }
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val last_piece = (piece_idx === UInt(n_pieces - 1))
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val sending = Reg(init = Bool(false))
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val in_last = Reg(Bool())
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when (io.in.fire()) {
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buffer := io.in.bits.data
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in_last := io.in.bits.last
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sending := Bool(true)
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}
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when (pkt_done) { sending := Bool(false) }
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io.out.valid := sending
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io.out.bits.data := pieces(piece_idx)
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io.out.bits.last := in_last && last_piece
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io.in.ready := !sending
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}
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class StreamExpander(win: Int, wout: Int) extends Module {
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require(win < wout, "Stream expander input width must be smaller than input width")
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require(wout % win == 0, "Stream narrower output width must be multiple of input width")
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val io = new Bundle {
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val in = Decoupled(new StreamChannel(win)).flip
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val out = Decoupled(new StreamChannel(wout))
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}
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val n_pieces = wout / win
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val buffer = Reg(Vec(n_pieces, UInt(width = win)))
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val last = Reg(Bool())
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val collecting = Reg(init = Bool(true))
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val (piece_idx, pkt_done) = Counter(io.in.fire(), n_pieces)
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when (io.in.fire()) { buffer(piece_idx) := io.in.bits.data }
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when (pkt_done) { last := io.in.bits.last; collecting := Bool(false) }
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when (io.out.fire()) { collecting := Bool(true) }
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io.in.ready := collecting
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io.out.valid := !collecting
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2016-08-01 02:13:52 +02:00
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io.out.bits.data := buffer.asUInt
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2016-01-22 02:39:57 +01:00
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io.out.bits.last := last
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}
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object StreamUtils {
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def connectStreams(a: StreamIO, b: StreamIO) {
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a.in <> b.out
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b.in <> a.out
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}
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2016-09-04 05:41:48 +02:00
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def roundUp(n: Int, d: Int) = ((n - 1) / d + 1) * d
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2016-01-22 02:39:57 +01:00
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}
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2016-09-04 05:41:48 +02:00
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class SerialIO(w: Int) extends Bundle {
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val out = Decoupled(UInt(width = w))
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val in = Decoupled(UInt(width = w)).flip
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override def cloneType = new SerialIO(w).asInstanceOf[this.type]
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2016-01-22 02:39:57 +01:00
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}
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2016-09-04 05:41:48 +02:00
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class Serializer[T <: Data](w: Int, typ: T) extends Module {
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2016-01-22 02:39:57 +01:00
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val io = new Bundle {
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val in = Decoupled(typ).flip
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2016-02-25 06:33:51 +01:00
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val out = Decoupled(Bits(width = w))
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2016-01-22 02:39:57 +01:00
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}
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2016-09-04 05:41:48 +02:00
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val narrower = Module(new StreamNarrower(StreamUtils.roundUp(typ.getWidth, w), w))
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2016-08-01 02:13:52 +02:00
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narrower.io.in.bits.data := io.in.bits.asUInt
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2016-01-22 02:39:57 +01:00
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narrower.io.in.bits.last := Bool(true)
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narrower.io.in.valid := io.in.valid
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io.in.ready := narrower.io.in.ready
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2016-02-25 06:33:51 +01:00
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io.out.valid := narrower.io.out.valid
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io.out.bits := narrower.io.out.bits.data
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narrower.io.out.ready := io.out.ready
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2016-01-22 02:39:57 +01:00
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}
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2016-09-04 05:41:48 +02:00
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class Deserializer[T <: Data](w: Int, typ: T) extends Module {
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2016-01-22 02:39:57 +01:00
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val io = new Bundle {
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2016-02-25 06:33:51 +01:00
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val in = Decoupled(Bits(width = w)).flip
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2016-01-22 02:39:57 +01:00
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val out = Decoupled(typ)
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}
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2016-09-04 05:41:48 +02:00
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val expander = Module(new StreamExpander(w, StreamUtils.roundUp(typ.getWidth, w)))
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2016-02-25 06:33:51 +01:00
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expander.io.in.valid := io.in.valid
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expander.io.in.bits.data := io.in.bits
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expander.io.in.bits.last := Bool(true)
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io.in.ready := expander.io.in.ready
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2016-01-22 02:39:57 +01:00
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io.out.valid := expander.io.out.valid
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2016-09-04 05:41:48 +02:00
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io.out.bits := typ.fromBits(expander.io.out.bits.data)
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2016-01-22 02:39:57 +01:00
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expander.io.out.ready := io.out.ready
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}
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