2016-01-06 05:04:49 +01:00
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package junctions
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import Chisel._
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import NastiConstants._
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import cde.Parameters
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class StreamChannel(w: Int) extends Bundle {
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val data = UInt(width = w)
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val last = Bool()
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override def cloneType = new StreamChannel(w).asInstanceOf[this.type]
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}
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class StreamIO(w: Int) extends Bundle {
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val out = Decoupled(new StreamChannel(w))
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val in = Decoupled(new StreamChannel(w)).flip
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override def cloneType = new StreamIO(w).asInstanceOf[this.type]
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}
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class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val stream = new StreamIO(w)
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}
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val streamSize = UInt(log2Up(w / 8))
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.size === streamSize,
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"read channel wrong size on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.ar.valid || io.nasti.ar.bits.len === UInt(0) ||
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io.nasti.ar.bits.burst === BURST_FIXED,
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2016-01-06 05:04:49 +01:00
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"read channel wrong burst type on stream")
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.size === streamSize,
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"write channel wrong size on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.aw.valid || io.nasti.aw.bits.len === UInt(0) ||
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io.nasti.aw.bits.burst === BURST_FIXED,
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2016-01-06 05:04:49 +01:00
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"write channel wrong burst type on stream")
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2016-02-15 18:48:35 +01:00
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assert(!io.nasti.w.valid || io.nasti.w.bits.strb.andR,
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"write channel cannot take partial writes")
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2016-01-06 05:04:49 +01:00
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val read_id = Reg(io.nasti.ar.bits.id)
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2016-02-15 18:48:35 +01:00
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val read_cnt = Reg(io.nasti.ar.bits.len)
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2016-01-06 05:04:49 +01:00
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val reading = Reg(init = Bool(false))
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io.nasti.ar.ready := !reading
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io.nasti.r.valid := reading && io.stream.in.valid
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io.nasti.r.bits := io.stream.in.bits
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io.nasti.r.bits.resp := UInt(0)
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io.nasti.r.bits.id := read_id
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io.stream.in.ready := reading && io.nasti.r.ready
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when (io.nasti.ar.fire()) {
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read_id := io.nasti.ar.bits.id
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2016-02-15 18:48:35 +01:00
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read_cnt := io.nasti.ar.bits.len
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2016-01-06 05:04:49 +01:00
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reading := Bool(true)
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}
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2016-02-15 18:48:35 +01:00
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when (io.nasti.r.fire()) {
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when (read_cnt === UInt(0)) {
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reading := Bool(false)
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} .otherwise {
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read_cnt := read_cnt - UInt(1)
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}
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2016-01-06 05:04:49 +01:00
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}
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val write_id = Reg(io.nasti.aw.bits.id)
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val writing = Reg(init = Bool(false))
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val write_resp = Reg(init = Bool(false))
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io.nasti.aw.ready := !writing && !write_resp
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io.nasti.w.ready := writing && io.stream.out.ready
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io.stream.out.valid := writing && io.nasti.w.valid
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io.stream.out.bits := io.nasti.w.bits
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io.nasti.b.valid := write_resp
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io.nasti.b.bits.resp := UInt(0)
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io.nasti.b.bits.id := write_id
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when (io.nasti.aw.fire()) {
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write_id := io.nasti.aw.bits.id
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writing := Bool(true)
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}
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when (io.nasti.w.fire() && io.nasti.w.bits.last) {
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writing := Bool(false)
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write_resp := Bool(true)
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}
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when (io.nasti.b.fire()) { write_resp := Bool(false) }
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}
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