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everything to get emulator working
2012-10-02 04:30:11 +02:00
# Makefile snippet used by emulator/vlsi/fpga backends
integrate updated rocket/uncore
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MODEL := Top
everything to get emulator working
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CXX := g++
CXXFLAGS := -O2
print stack trace if elaboration fails
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SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
everything to get emulator working
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#--------------------------------------------------------------------
# Tests
#--------------------------------------------------------------------
# Globally installed assembly tests
global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests
global_asm_tests = \
riscv_ipi \
riscv_add \
riscv_addi \
riscv_amoadd_d \
riscv_amoadd_w \
riscv_amoand_d \
riscv_amoand_w \
riscv_amoor_d \
riscv_amoor_w \
riscv_amoswap_d \
riscv_amoswap_w \
riscv_amomax_d \
riscv_amomax_w \
riscv_amomaxu_d \
riscv_amomaxu_w \
riscv_amomin_d \
riscv_amomin_w \
riscv_amominu_d \
riscv_amominu_w \
riscv_fence_i \
riscv_sb \
riscv_sd \
riscv_sh \
riscv_sw \
riscv_addiw \
riscv_addw \
riscv_and \
riscv_andi \
riscv_beq \
riscv_bge \
riscv_bgeu \
riscv_blt \
riscv_bltu \
riscv_bne \
riscv_div \
riscv_divu \
riscv_divuw \
riscv_divw \
riscv_j \
riscv_jal \
riscv_jalr \
riscv_jalr_j \
riscv_jalr_r \
riscv_lb \
riscv_lbu \
riscv_ld \
riscv_lh \
riscv_lhu \
riscv_lui \
riscv_lw \
riscv_lwu \
riscv_mul \
riscv_mulh \
riscv_mulhsu \
riscv_mulhu \
riscv_mulw \
riscv_or \
riscv_ori \
riscv_rdnpc \
riscv_rem \
riscv_remu \
riscv_remuw \
riscv_remw \
riscv_simple \
riscv_sll \
riscv_slli \
riscv_slliw \
riscv_sllw \
riscv_slt \
riscv_slti \
riscv_sltiu \
riscv_sltu \
riscv_sra \
riscv_srai \
riscv_sraiw \
riscv_sraw \
riscv_srliw \
riscv_srlw \
riscv_sub \
riscv_subw \
riscv_xor \
riscv_xori \
riscv_fp_ldst \
riscv_fp_move \
riscv_fsgnj \
riscv_fcmp \
riscv_fcvt \
riscv_fcvt_w \
riscv_fadd \
riscv_fmin \
riscv_fmadd \
riscv_fp_structural \
global_asm_vm_tests = \
riscv_add_vm \
riscv_addi_vm \
riscv_amoadd_d_vm \
riscv_amoadd_w_vm \
riscv_amoand_d_vm \
riscv_amoand_w_vm \
riscv_amoor_d_vm \
riscv_amoor_w_vm \
riscv_amoswap_d_vm \
riscv_amoswap_w_vm \
riscv_amomax_d_vm \
riscv_amomax_w_vm \
riscv_amomaxu_d_vm \
riscv_amomaxu_w_vm \
riscv_amomin_d_vm \
riscv_amomin_w_vm \
riscv_amominu_d_vm \
riscv_amominu_w_vm \
riscv_fence_i_vm \
riscv_sb_vm \
riscv_sd_vm \
riscv_sh_vm \
riscv_sw_vm \
riscv_addiw_vm \
riscv_addw_vm \
riscv_and_vm \
riscv_andi_vm \
riscv_beq_vm \
riscv_bge_vm \
riscv_bgeu_vm \
riscv_blt_vm \
riscv_bltu_vm \
riscv_bne_vm \
riscv_div_vm \
riscv_divu_vm \
riscv_divuw_vm \
riscv_divw_vm \
riscv_j_vm \
riscv_jal_vm \
riscv_jalr_vm \
riscv_jalr_j_vm \
riscv_jalr_r_vm \
riscv_lb_vm \
riscv_lbu_vm \
riscv_ld_vm \
riscv_lh_vm \
riscv_lhu_vm \
riscv_lui_vm \
riscv_lw_vm \
riscv_lwu_vm \
riscv_mul_vm \
riscv_mulh_vm \
riscv_mulhsu_vm \
riscv_mulhu_vm \
riscv_mulw_vm \
riscv_or_vm \
riscv_ori_vm \
riscv_rdnpc_vm \
riscv_rem_vm \
riscv_remu_vm \
riscv_remuw_vm \
riscv_remw_vm \
riscv_sll_vm \
riscv_slli_vm \
riscv_slliw_vm \
riscv_sllw_vm \
riscv_slt_vm \
riscv_slti_vm \
riscv_sltiu_vm \
riscv_sltu_vm \
riscv_sra_vm \
riscv_srai_vm \
riscv_sraiw_vm \
riscv_sraw_vm \
riscv_srliw_vm \
riscv_srlw_vm \
riscv_sub_vm \
riscv_subw_vm \
riscv_xor_vm \
riscv_xori_vm \
riscv_fp_ldst_vm \
riscv_fp_move_vm \
riscv_fsgnj_vm \
riscv_fcmp_vm \
riscv_fcvt_vm \
riscv_fcvt_w_vm \
riscv_fadd_vm \
riscv_fmin_vm \
riscv_fmadd_vm \
riscv_fp_structural_vm \
global_vecasm_tests = \
riscv_vec_wakeup_vec \
riscv_vec_fence_vec \
riscv_vec_utidx_vec \
riscv_vec_vmsv_vec \
riscv_vec_vmvv_vec \
riscv_vec_vfmvv_vec \
riscv_vec_movz_vec \
riscv_vec_movn_vec \
riscv_vec_fmovz_vec \
riscv_vec_fmovn_vec \
riscv_vec_ld_vec \
riscv_vec_lw_vec \
riscv_vec_lwu_vec \
riscv_vec_lh_vec \
riscv_vec_lhu_vec \
riscv_vec_lb_vec \
riscv_vec_lbu_vec \
riscv_vec_sd_vec \
riscv_vec_sw_vec \
riscv_vec_sh_vec \
riscv_vec_sb_vec \
riscv_vec_fld_vec \
riscv_vec_flw_vec \
riscv_vec_fsd_vec \
riscv_vec_fsw_vec \
riscv_vec_fcvt-d-l_vec \
riscv_vec_vvadd_d_vec \
riscv_vec_vvadd_fw_vec \
riscv_vec_vvadd_fd_vec \
riscv_vec_vvadd_w_vec \
riscv_vec_vvmul_d_vec \
riscv_vec_amoadd_d_vec \
riscv_vec_amoswap_d_vec \
riscv_vec_amoand_d_vec \
riscv_vec_amoor_d_vec \
riscv_vec_amomax_d_vec \
riscv_vec_amomin_d_vec \
riscv_vec_amomaxu_d_vec \
riscv_vec_amominu_d_vec \
riscv_vec_amoadd_w_vec \
riscv_vec_amoswap_w_vec \
riscv_vec_amoand_w_vec \
riscv_vec_amoor_w_vec \
riscv_vec_amomax_w_vec \
riscv_vec_amomin_w_vec \
riscv_vec_amomaxu_w_vec \
riscv_vec_amominu_w_vec \
riscv_vec_imul_vec \
riscv_vec_fma_vec \
riscv_mul_vec \
riscv_mulw_vec \
riscv_mulh_vec \
riscv_mulhu_vec \
riscv_mulhsu_vec \
riscv_addi_vec \
riscv_add_vec \
riscv_addiw_vec \
riscv_addw_vec \
riscv_and_vec \
riscv_andi_vec \
riscv_lui_vec \
riscv_or_vec \
riscv_ori_vec \
riscv_slt_vec \
riscv_sltu_vec \
riscv_slti_vec \
riscv_sltiu_vec \
riscv_slli_vec \
riscv_sll_vec \
riscv_slliw_vec \
riscv_sllw_vec \
riscv_srai_vec \
riscv_sra_vec \
riscv_sraiw_vec \
riscv_sraw_vec \
riscv_srli_vec \
riscv_srl_vec \
riscv_srliw_vec \
riscv_srlw_vec \
riscv_sub_vec \
riscv_subw_vec \
riscv_xor_vec \
riscv_xori_vec \
riscv_fadd_vec \
riscv_fsgnj_vec \
riscv_fmin_vec \
riscv_fmadd_vec \
riscv_fcvt_w_vec \
riscv_fcvt_vec \
riscv_fcmp_vec \
riscv_vec_xcpt_ma_inst \
riscv_vec_xcpt_illegal \
fix tab
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riscv_vec_xcpt_illegal_vt_regid \
riscv_vec_xcpt_illegal_tvec_regid \
everything to get emulator working
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riscv_vec_ma_vld \
riscv_vec_ma_vsd \
riscv_vec_ma_utld \
riscv_vec_ma_utsd \
riscv_vec_illegal_tvec \
global_vecasm_vm_tests = \
riscv_vec_wakeup_vec_vm \
riscv_vec_fence_vec_vm \
riscv_vec_utidx_vec_vm \
riscv_vec_vmsv_vec_vm \
riscv_vec_vmvv_vec_vm \
riscv_vec_vfmvv_vec_vm \
riscv_vec_movz_vec_vm \
riscv_vec_movn_vec_vm \
riscv_vec_fmovz_vec_vm \
riscv_vec_fmovn_vec_vm \
riscv_vec_ld_vec_vm \
riscv_vec_lw_vec_vm \
riscv_vec_lwu_vec_vm \
riscv_vec_lh_vec_vm \
riscv_vec_lhu_vec_vm \
riscv_vec_lb_vec_vm \
riscv_vec_lbu_vec_vm \
riscv_vec_sd_vec_vm \
riscv_vec_sw_vec_vm \
riscv_vec_sh_vec_vm \
riscv_vec_sb_vec_vm \
riscv_vec_fld_vec_vm \
riscv_vec_flw_vec_vm \
riscv_vec_fsd_vec_vm \
riscv_vec_fsw_vec_vm \
riscv_vec_fcvt-d-l_vec_vm \
riscv_vec_vvadd_d_vec_vm \
riscv_vec_vvadd_fw_vec_vm \
riscv_vec_vvadd_fd_vec_vm \
riscv_vec_vvadd_w_vec_vm \
riscv_vec_vvmul_d_vec_vm \
riscv_vec_amoadd_d_vec_vm \
riscv_vec_amoswap_d_vec_vm \
riscv_vec_amoand_d_vec_vm \
riscv_vec_amoor_d_vec_vm \
riscv_vec_amomax_d_vec_vm \
riscv_vec_amomin_d_vec_vm \
riscv_vec_amomaxu_d_vec_vm \
riscv_vec_amominu_d_vec_vm \
riscv_vec_amoadd_w_vec_vm \
riscv_vec_amoswap_w_vec_vm \
riscv_vec_amoand_w_vec_vm \
riscv_vec_amoor_w_vec_vm \
riscv_vec_amomax_w_vec_vm \
riscv_vec_amomin_w_vec_vm \
riscv_vec_amomaxu_w_vec_vm \
riscv_vec_amominu_w_vec_vm \
riscv_vec_imul_vec_vm \
riscv_vec_fma_vec_vm \
riscv_mul_vec_vm \
riscv_mulw_vec_vm \
riscv_mulh_vec_vm \
riscv_mulhu_vec_vm \
riscv_mulhsu_vec_vm \
riscv_addi_vec_vm \
riscv_add_vec_vm \
riscv_addiw_vec_vm \
riscv_addw_vec_vm \
riscv_and_vec_vm \
riscv_andi_vec_vm \
riscv_lui_vec_vm \
riscv_or_vec_vm \
riscv_ori_vec_vm \
riscv_slt_vec_vm \
riscv_sltu_vec_vm \
riscv_slti_vec_vm \
riscv_sltiu_vec_vm \
riscv_slli_vec_vm \
riscv_sll_vec_vm \
riscv_slliw_vec_vm \
riscv_sllw_vec_vm \
riscv_srai_vec_vm \
riscv_sra_vec_vm \
riscv_sraiw_vec_vm \
riscv_sraw_vec_vm \
riscv_srli_vec_vm \
riscv_srl_vec_vm \
riscv_srliw_vec_vm \
riscv_srlw_vec_vm \
riscv_sub_vec_vm \
riscv_subw_vec_vm \
riscv_xor_vec_vm \
riscv_xori_vec_vm \
riscv_fadd_vec_vm \
riscv_fsgnj_vec_vm \
riscv_fmin_vec_vm \
riscv_fmadd_vec_vm \
riscv_fcvt_w_vec_vm \
riscv_fcvt_vec_vm \
riscv_fcmp_vec_vm \
global_vecasm_timer_tests = \
riscv_vec_wakeup_vec_timer \
riscv_vec_fence_vec_timer \
riscv_vec_vvadd_d_vec_timer \
riscv_vec_vvadd_fw_vec_timer \
riscv_vec_vvadd_fd_vec_timer \
riscv_vec_vvadd_w_vec_timer \
riscv_vec_vvmul_d_vec_timer \
riscv_vec_fcvt-d-l_vec_timer \
riscv_vec_utidx_vec_timer \
riscv_vec_vmvv_vec_timer \
riscv_vec_vmsv_vec_timer \
riscv_vec_vfmvv_vec_timer \
riscv_vec_movz_vec_timer \
riscv_vec_movn_vec_timer \
riscv_vec_fmovz_vec_timer \
riscv_vec_fmovn_vec_timer \
riscv_vec_ld_vec_timer \
riscv_vec_lw_vec_timer \
riscv_vec_lwu_vec_timer \
riscv_vec_lh_vec_timer \
riscv_vec_lhu_vec_timer \
riscv_vec_lb_vec_timer \
riscv_vec_lbu_vec_timer \
riscv_vec_sd_vec_timer \
riscv_vec_sw_vec_timer \
riscv_vec_sh_vec_timer \
riscv_vec_sb_vec_timer \
riscv_vec_fld_vec_timer \
riscv_vec_flw_vec_timer \
riscv_vec_fsd_vec_timer \
riscv_vec_fsw_vec_timer \
riscv_vec_amoadd_d_vec_timer \
riscv_vec_amoswap_d_vec_timer \
riscv_vec_amoand_d_vec_timer \
riscv_vec_amoor_d_vec_timer \
riscv_vec_amomax_d_vec_timer \
riscv_vec_amomin_d_vec_timer \
riscv_vec_amomaxu_d_vec_timer \
riscv_vec_amominu_d_vec_timer \
riscv_vec_amoadd_w_vec_timer \
riscv_vec_amoswap_w_vec_timer \
riscv_vec_amoand_w_vec_timer \
riscv_vec_amoor_w_vec_timer \
riscv_vec_amomax_w_vec_timer \
riscv_vec_amomin_w_vec_timer \
riscv_vec_amomaxu_w_vec_timer \
riscv_vec_amominu_w_vec_timer \
riscv_vec_imul_vec_timer \
riscv_vec_fma_vec_timer \
riscv_mul_vec_timer \
riscv_mulw_vec_timer \
riscv_mulh_vec_timer \
riscv_mulhu_vec_timer \
riscv_mulhsu_vec_timer \
riscv_addi_vec_timer \
riscv_add_vec_timer \
riscv_addiw_vec_timer \
riscv_addw_vec_timer \
riscv_and_vec_timer \
riscv_andi_vec_timer \
riscv_lui_vec_timer \
riscv_or_vec_timer \
riscv_ori_vec_timer \
riscv_slt_vec_timer \
riscv_sltu_vec_timer \
riscv_slti_vec_timer \
riscv_sltiu_vec_timer \
riscv_slli_vec_timer \
riscv_sll_vec_timer \
riscv_slliw_vec_timer \
riscv_sllw_vec_timer \
riscv_srai_vec_timer \
riscv_sra_vec_timer \
riscv_sraiw_vec_timer \
riscv_sraw_vec_timer \
riscv_srli_vec_timer \
riscv_srl_vec_timer \
riscv_srliw_vec_timer \
riscv_srlw_vec_timer \
riscv_sub_vec_timer \
riscv_subw_vec_timer \
riscv_xor_vec_timer \
riscv_xori_vec_timer \
riscv_fadd_vec_timer \
riscv_fsgnj_vec_timer \
riscv_fmin_vec_timer \
riscv_fmadd_vec_timer \
riscv_fcvt_w_vec_timer \
riscv_fcvt_vec_timer \
riscv_fcmp_vec_timer \
# Globally installed benchmarks
global_bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks
global_bmarks = \
median.riscv \
multiply.riscv \
qsort.riscv \
towers.riscv \
vvadd.riscv \
dgemm.riscv \
first crack at continuous compilation/testing flow try it out: cd emulator; make test
2012-10-19 13:09:07 +02:00
dhrystone.riscv \
update to new rocket; retime fpu in dc-syn
2012-11-05 01:43:02 +01:00
spmv.riscv \
everything to get emulator working
2012-10-02 04:30:11 +02:00
global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
global_vec_bmarks = \
fix tab
2012-10-11 21:09:49 +02:00
ubmark-vvadd \
ubmark-bin-search \
ubmark-cmplx-mult \
ubmark-masked-filter \
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