2017-02-09 22:59:09 +01:00
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// See LICENSE.SiFive for license details.
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.tile
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2017-02-09 22:59:09 +01:00
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import Chisel._
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2017-07-07 19:48:16 +02:00
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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2017-02-09 22:59:09 +01:00
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case object SharedMemoryTLEdge extends Field[TLEdgeOut]
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case object TileKey extends Field[TileParams]
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2017-04-28 00:22:52 +02:00
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case object ResetVectorBits extends Field[Int]
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case object MaxHartIdBits extends Field[Int]
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2017-02-09 22:59:09 +01:00
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trait TileParams {
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val core: CoreParams
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val icache: Option[ICacheParams]
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val dcache: Option[DCacheParams]
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val rocc: Seq[RoCCParams]
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val btb: Option[BTBParams]
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2017-09-20 07:59:28 +02:00
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val trace: Boolean
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2017-02-09 22:59:09 +01:00
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}
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trait HasTileParameters {
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implicit val p: Parameters
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2017-09-02 02:50:54 +02:00
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def tileParams: TileParams = p(TileKey)
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def usingVM: Boolean = tileParams.core.useVM
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def usingUser: Boolean = tileParams.core.useUser || usingVM
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def usingDebug: Boolean = tileParams.core.useDebug
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def usingRoCC: Boolean = !tileParams.rocc.isEmpty
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def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
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def usingPTW: Boolean = usingVM
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def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined
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def xLen: Int = p(XLen)
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def xBytes: Int = xLen / 8
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def iLen: Int = 32
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2017-09-02 02:50:54 +02:00
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def pgIdxBits: Int = 12
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def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
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def vaddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
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def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
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def vpnBits: Int = vaddrBits - pgIdxBits
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def ppnBits: Int = paddrBits - pgIdxBits
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def pgLevels: Int = p(PgLevels)
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def asIdBits: Int = p(ASIdBits)
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def vpnBitsExtended: Int = vpnBits + (vaddrBits < xLen).toInt
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def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
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def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
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def hartIdLen: Int = p(MaxHartIdBits)
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def resetVectorLen: Int = paddrBits min vaddrBitsExtended
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2017-02-09 22:59:09 +01:00
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def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
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}
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abstract class BareTile(implicit p: Parameters) extends LazyModule
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abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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2017-04-28 00:22:52 +02:00
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/** Uses TileLink master port to connect caches and accelerators to the coreplex */
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trait HasTileLinkMasterPort {
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2017-02-09 22:59:09 +01:00
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implicit val p: Parameters
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val module: HasTileLinkMasterPortModule
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val masterNode = TLOutputNode()
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2017-05-17 01:12:01 +02:00
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val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
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masterNode := tileBus.node
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2017-02-09 22:59:09 +01:00
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}
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trait HasTileLinkMasterPortBundle {
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val outer: HasTileLinkMasterPort
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val master = outer.masterNode.bundleOut
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}
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trait HasTileLinkMasterPortModule {
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val outer: HasTileLinkMasterPort
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val io: HasTileLinkMasterPortBundle
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}
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2017-04-28 00:22:52 +02:00
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/** Some other standard inputs */
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2017-09-02 02:50:54 +02:00
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trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
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val hartid = UInt(INPUT, hartIdLen)
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val reset_vector = UInt(INPUT, resetVectorLen)
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2017-04-28 00:22:52 +02:00
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}
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2017-09-20 07:59:28 +02:00
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trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
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val trace = tileParams.trace.option(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput)
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}
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2017-04-28 00:22:52 +02:00
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/** Base class for all Tiles that use TileLink */
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2017-02-09 22:59:09 +01:00
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abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
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2017-07-07 19:48:16 +02:00
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with HasTileParameters
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with HasTileLinkMasterPort {
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2017-02-09 22:59:09 +01:00
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override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
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}
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class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
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2017-03-30 04:14:04 +02:00
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with HasTileLinkMasterPortBundle
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2017-04-28 00:22:52 +02:00
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with HasExternallyDrivenTileConstants
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2017-09-20 07:59:28 +02:00
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with CanHaveInstructionTracePort
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2017-02-09 22:59:09 +01:00
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class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
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2017-09-02 02:50:54 +02:00
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with HasTileParameters
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with HasTileLinkMasterPortModule {
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require(xLen == 32 || xLen == 64)
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require(paddrBits <= maxPAddrBits)
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require(resetVectorLen <= xLen)
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require(resetVectorLen <= vaddrBitsExtended)
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}
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