2017-02-04 01:20:27 +01:00
|
|
|
// See LICENSE.SiFive for license details.
|
|
|
|
|
2017-07-07 19:48:16 +02:00
|
|
|
package freechips.rocketchip.devices.tilelink
|
2017-02-04 01:20:27 +01:00
|
|
|
|
|
|
|
import Chisel._
|
2017-07-23 17:31:04 +02:00
|
|
|
import freechips.rocketchip.config.{Field, Parameters}
|
|
|
|
import freechips.rocketchip.coreplex.HasMemoryBus
|
2017-07-07 19:48:16 +02:00
|
|
|
import freechips.rocketchip.diplomacy._
|
|
|
|
import freechips.rocketchip.tilelink._
|
2017-02-04 01:20:27 +01:00
|
|
|
|
2017-07-18 06:48:31 +02:00
|
|
|
class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
2017-02-04 01:20:27 +01:00
|
|
|
{
|
|
|
|
val node = TLManagerNode(Seq(TLManagerPortParameters(
|
|
|
|
Seq(TLManagerParameters(
|
|
|
|
address = List(address),
|
2017-07-18 06:48:31 +02:00
|
|
|
resources = resources,
|
2017-02-04 01:20:27 +01:00
|
|
|
regionType = RegionType.UNCACHED,
|
|
|
|
executable = executable,
|
|
|
|
supportsGet = TransferSizes(1, beatBytes),
|
|
|
|
supportsPutPartial = TransferSizes(1, beatBytes),
|
|
|
|
supportsPutFull = TransferSizes(1, beatBytes),
|
|
|
|
fifoId = Some(0))), // requests are handled in order
|
|
|
|
beatBytes = beatBytes,
|
|
|
|
minLatency = 1))) // no bypass needed for this device
|
|
|
|
|
|
|
|
lazy val module = new LazyModuleImp(this) {
|
|
|
|
val io = new Bundle {
|
|
|
|
val in = node.bundleIn
|
|
|
|
}
|
|
|
|
|
|
|
|
val in = io.in(0)
|
|
|
|
val edge = node.edgesIn(0)
|
|
|
|
|
|
|
|
val a = Queue(in.a, 2)
|
|
|
|
val hasData = edge.hasData(a.bits)
|
|
|
|
|
|
|
|
a.ready := in.d.ready
|
|
|
|
in.d.valid := a.valid
|
2017-07-27 01:01:21 +02:00
|
|
|
in.d.bits := edge.AccessAck(a.bits)
|
2017-02-04 01:20:27 +01:00
|
|
|
in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
|
|
|
|
|
|
|
|
// Tie off unused channels
|
|
|
|
in.b.valid := Bool(false)
|
|
|
|
in.c.ready := Bool(true)
|
|
|
|
in.e.ready := Bool(true)
|
|
|
|
}
|
|
|
|
}
|
2017-07-23 17:31:04 +02:00
|
|
|
|
|
|
|
/* Specifies the location of the Zero device */
|
|
|
|
case class ZeroParams(base: Long, size: Long, beatBytes: Int)
|
|
|
|
case object ZeroParams extends Field[ZeroParams]
|
|
|
|
|
|
|
|
/** Adds a /dev/null slave that generates zero-filled responses to reads */
|
|
|
|
trait HasMemoryZeroSlave extends HasMemoryBus {
|
|
|
|
private val params = p(ZeroParams)
|
|
|
|
private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
|
|
|
|
|
|
|
|
val zeros = memBuses.map(_.toVariableWidthSlave).zipWithIndex.map { case (node, channel) =>
|
|
|
|
val channels = memBuses.size
|
|
|
|
val base = AddressSet(params.base, params.size-1)
|
|
|
|
val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
|
|
|
|
val address = base.intersect(filter).get
|
|
|
|
val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
|
|
|
|
zero.node := node
|
|
|
|
zero
|
|
|
|
}
|
|
|
|
}
|