49 lines
1.2 KiB
Scala
49 lines
1.2 KiB
Scala
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.util
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import Chisel._
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/** Takes in data on one decoupled interface and broadcasts it
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* to N decoupled output interfaces.
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*/
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class Broadcaster[T <: Data](typ: T, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(typ).flip
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val out = Vec(n, Decoupled(typ))
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}
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require (n > 0)
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if (n == 1) {
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io.out.head <> io.in
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} else {
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val idx = Reg(init = UInt(0, log2Up(n)))
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val save = Reg(typ)
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io.out.head.valid := idx === UInt(0) && io.in.valid
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io.out.head.bits := io.in.bits
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for (i <- 1 until n) {
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io.out(i).valid := idx === UInt(i)
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io.out(i).bits := save
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}
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io.in.ready := io.out.head.ready && idx === UInt(0)
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when (io.in.fire()) { save := io.in.bits }
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when (io.out(idx).fire()) {
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when (idx === UInt(n - 1)) { idx := UInt(0) }
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.otherwise { idx := idx + UInt(1) }
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}
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}
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}
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object Broadcaster {
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def apply[T <: Data](in: DecoupledIO[T], n: Int): Vec[DecoupledIO[T]] = {
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val split = Module(new Broadcaster(in.bits, n))
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split.io.in <> in
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split.io.out
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}
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}
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