46 lines
1.4 KiB
Scala
46 lines
1.4 KiB
Scala
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package rocket
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import Chisel._
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import Node._
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import Constants._
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class Tile extends Component
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{
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val io = new Bundle {
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val tilelink = new ioTileLink
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val host = new ioHTIF
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}
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val cpu = new rocketProc(resetSignal = io.host.reset)
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val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
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val icache_pf = new rocketIPrefetcher
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val dcache = new HellaCacheUniproc
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val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init)
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io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data)
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arbiter.io.mem.xact_abort <> Queue(io.tilelink.xact_abort)
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arbiter.io.mem.xact_rep <> Pipe(io.tilelink.xact_rep)
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io.tilelink.xact_finish <> Queue(arbiter.io.mem.xact_finish)
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dcache.io.mem.probe_req <> Queue(io.tilelink.probe_req)
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io.tilelink.probe_rep <> Queue(dcache.io.mem.probe_rep, 1)
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io.tilelink.probe_rep_data <> Queue(dcache.io.mem.probe_rep_data)
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if (HAVE_VEC)
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{
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val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
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arbiter.io.requestor(2) <> vicache.io.mem
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cpu.io.vimem <> vicache.io.cpu
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}
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cpu.io.host <> io.host
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icache_pf.io.invalidate := cpu.io.imem.invalidate
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icache.io.mem <> icache_pf.io.icache
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cpu.io.imem <> icache.io.cpu
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cpu.io.dmem <> dcache.io.cpu
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}
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