2011-11-10 06:54:11 +01:00
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package Top
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{
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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2011-11-10 09:50:09 +01:00
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// interface between DTLB and pipeline
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2011-11-10 06:54:11 +01:00
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class ioDTLB_CPU(view: List[String] = null) extends Bundle(view)
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{
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// status bits (from PCR), to check current permission and whether VM is enabled
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val status = Bits(17, 'input);
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// invalidate all TLB entries
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val invalidate = Bool('input);
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// lookup requests
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val req_val = Bool('input);
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val req_cmd = Bits(4, 'input); // load/store/amo
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val req_rdy = Bool('output);
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val req_asid = Bits(ASID_BITS, 'input);
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2011-11-12 03:18:47 +01:00
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val req_vpn = UFix(VPN_BITS, 'input);
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2011-11-10 06:54:11 +01:00
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// lookup responses
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2011-11-13 00:00:45 +01:00
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val resp_busy = Bool('output);
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2011-11-10 09:50:09 +01:00
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val resp_miss = Bool('output);
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2011-11-12 03:18:47 +01:00
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// val resp_val = Bool('output);
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val resp_ppn = UFix(PPN_BITS, 'output);
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2011-11-10 09:50:09 +01:00
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val xcpt_ld = Bool('output);
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val xcpt_st = Bool('output);
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2011-11-10 06:54:11 +01:00
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}
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class ioDTLB extends Bundle
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{
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val cpu = new ioDTLB_CPU();
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val ptw = new ioTLB_PTW();
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}
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class rocketDTLB(entries: Int) extends Component
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{
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val io = new ioDTLB();
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2011-11-12 03:18:47 +01:00
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val addr_bits = ceil(log10(entries)/log10(2)).toInt;
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2011-11-10 06:54:11 +01:00
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val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() };
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val state = Reg(resetVal = s_ready);
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2011-11-12 03:18:47 +01:00
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val r_cpu_req_vpn = Reg(resetVal = Bits(0, VPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
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val r_cpu_req_asid = Reg(resetVal = Bits(0,ASID_BITS));
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val r_refill_tag = Reg(resetVal = Bits(0,ASID_BITS+VPN_BITS));
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val r_refill_waddr = Reg(resetVal = UFix(0,addr_bits));
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val repl_count = Reg(resetVal = UFix(0,addr_bits));
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_vpn <== io.cpu.req_vpn;
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r_cpu_req_cmd <== io.cpu.req_cmd;
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r_cpu_req_asid <== io.cpu.req_asid;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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2011-11-10 06:54:11 +01:00
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2011-11-12 03:18:47 +01:00
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val req_load = (r_cpu_req_cmd === M_XRD);
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val req_store = (r_cpu_req_cmd === M_XWR);
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2011-11-13 00:00:45 +01:00
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val req_flush = (r_cpu_req_cmd === M_FLA);
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2011-11-12 03:18:47 +01:00
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// val req_amo = io.cpu.req_cmd(3).toBool;
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2011-11-10 06:54:11 +01:00
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2011-11-12 03:18:47 +01:00
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS);
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2011-11-10 06:54:11 +01:00
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val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
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2011-11-10 20:26:13 +01:00
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tag_cam.io.clear := io.cpu.invalidate;
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2011-11-10 06:54:11 +01:00
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tag_cam.io.tag := lookup_tag;
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2011-11-13 00:47:47 +01:00
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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2011-11-10 06:54:11 +01:00
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tag_cam.io.write_tag := r_refill_tag;
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tag_cam.io.write_addr := r_refill_waddr;
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2011-11-12 03:18:47 +01:00
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val tag_hit = tag_cam.io.hit;
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2011-11-11 02:41:22 +01:00
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val tag_hit_addr = tag_cam.io.hit_addr;
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2011-11-10 06:54:11 +01:00
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// extract fields from status register
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2011-11-11 02:41:22 +01:00
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val status_s = io.cpu.status(SR_S).toBool; // user/supervisor mode
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val status_u = !status_s;
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val status_vm = io.cpu.status(SR_VM).toBool // virtual memory enable
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2011-11-10 06:54:11 +01:00
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// extract fields from PT permission bits
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val ptw_perm_ur = io.ptw.resp_perm(1);
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val ptw_perm_uw = io.ptw.resp_perm(2);
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val ptw_perm_sr = io.ptw.resp_perm(4);
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val ptw_perm_sw = io.ptw.resp_perm(5);
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// permission bit arrays
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2011-11-12 03:18:47 +01:00
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val ur_array = Reg(resetVal = Bits(0, entries)); // user read permission
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val uw_array = Reg(resetVal = Bits(0, entries)); // user write permission
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val sr_array = Reg(resetVal = Bits(0, entries)); // supervisor read permission
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val sw_array = Reg(resetVal = Bits(0, entries)); // supervisor write permission
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2011-11-10 06:54:11 +01:00
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when (io.ptw.resp_val) {
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ur_array <== ur_array.bitSet(r_refill_waddr, ptw_perm_ur);
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2011-11-11 02:41:22 +01:00
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uw_array <== uw_array.bitSet(r_refill_waddr, ptw_perm_uw);
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2011-11-10 06:54:11 +01:00
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sr_array <== sr_array.bitSet(r_refill_waddr, ptw_perm_sr);
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sw_array <== sw_array.bitSet(r_refill_waddr, ptw_perm_sw);
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}
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// when the page table lookup reports an error, set all permission
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// bits to 0 so the next access will cause an exception
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when (io.ptw.resp_err) {
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ur_array <== ur_array.bitSet(r_refill_waddr, Bool(false));
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2011-11-11 02:41:22 +01:00
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uw_array <== uw_array.bitSet(r_refill_waddr, Bool(false));
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2011-11-10 06:54:11 +01:00
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sr_array <== sr_array.bitSet(r_refill_waddr, Bool(false));
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sw_array <== sw_array.bitSet(r_refill_waddr, Bool(false));
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}
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// high if there are any unused (invalid) entries in the TLB
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2011-11-10 20:26:13 +01:00
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val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries));
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2011-11-10 06:54:11 +01:00
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val ie_enc = new priorityEncoder(entries);
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2011-11-10 20:26:13 +01:00
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ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix;
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2011-11-10 06:54:11 +01:00
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val ie_addr = ie_enc.io.out;
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val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
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2011-11-13 00:00:45 +01:00
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val lookup_hit = (state === s_ready) && r_cpu_req_val && !req_flush && tag_hit;
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val lookup_miss = (state === s_ready) && r_cpu_req_val && !req_flush && !tag_hit;
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2011-11-11 02:41:22 +01:00
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val tlb_hit = status_vm && lookup_hit;
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val tlb_miss = status_vm && lookup_miss;
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2011-11-12 03:18:47 +01:00
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// currently replace TLB entries in LIFO order
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// TODO: implement LRU replacement policy
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2011-11-11 02:41:22 +01:00
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when (tlb_miss) {
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2011-11-10 06:54:11 +01:00
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r_refill_tag <== lookup_tag;
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r_refill_waddr <== repl_waddr;
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when (!invalid_entry) {
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repl_count <== repl_count + UFix(1);
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}
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}
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2011-11-11 02:41:22 +01:00
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// FIXME: add check for out of range physical addresses (>MEMSIZE)
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2011-11-10 09:50:09 +01:00
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io.cpu.xcpt_ld :=
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2011-11-11 02:41:22 +01:00
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tlb_hit && req_load &&
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((status_s && !sr_array(tag_hit_addr).toBool) ||
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(status_u && !ur_array(tag_hit_addr).toBool));
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2011-11-10 06:54:11 +01:00
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2011-11-10 09:50:09 +01:00
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io.cpu.xcpt_st :=
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2011-11-11 02:41:22 +01:00
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tlb_hit && req_store &&
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((status_s && !sw_array(tag_hit_addr).toBool) ||
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(status_u && !uw_array(tag_hit_addr).toBool));
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2011-11-10 06:54:11 +01:00
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2011-11-13 00:00:45 +01:00
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
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io.cpu.resp_busy := tlb_miss || (state != s_ready);
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2011-11-11 02:41:22 +01:00
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io.cpu.resp_miss := tlb_miss;
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2011-11-13 00:00:45 +01:00
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io.cpu.resp_ppn :=
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Mux(status_vm, Mux(req_flush, Bits(0,PPN_BITS), tag_ram(tag_hit_addr)),
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r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
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2011-11-10 06:54:11 +01:00
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io.ptw.req_val := (state === s_request);
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io.ptw.req_vpn := r_refill_tag(VPN_BITS-1,0);
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// control state machine
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switch (state) {
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is (s_ready) {
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2011-11-11 02:41:22 +01:00
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when (tlb_miss) {
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2011-11-10 06:54:11 +01:00
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state <== s_request;
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}
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}
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is (s_request) {
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when (io.ptw.req_rdy) {
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state <== s_wait;
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}
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}
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is (s_wait) {
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when (io.ptw.resp_val || io.ptw.resp_err) {
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state <== s_ready;
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}
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}
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}
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}
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}
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